Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test/test_bandwidth: review, cleanup, fix typo.

This commit is contained in:
Florent Kermarrec 2020-04-14 21:57:40 +02:00
parent 907ef73971
commit de55a8e170
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
test/test_bandwidth.py
View File

@ -89,7 +89,7 @@ class TestBandwidth(unittest.TestCase):
def test_requires_update_to_copy_the_data(self): def test_requires_update_to_copy_the_data(self):
# Verify that command counts are copied to CSRs only after `update`. # Verify that command counts are copied to CSRs only after `update`.
def main_generator(dut): def main_generator(dut):
nreads = (yield from dut.bandwidth.nreads.read()) nreads = (yield from dut.bandwidth.nreads.read())
nwrites = (yield from dut.bandwidth.nwrites.read()) nwrites = (yield from dut.bandwidth.nwrites.read())
self.assertEqual(nreads, 0) self.assertEqual(nreads, 0)
self.assertEqual(nwrites, 0) self.assertEqual(nwrites, 0)
@ -98,7 +98,7 @@ class TestBandwidth(unittest.TestCase):
for _ in range(2**6): for _ in range(2**6):
yield yield
nreads = (yield from dut.bandwidth.nreads.read()) nreads = (yield from dut.bandwidth.nreads.read())
nwrites = (yield from dut.bandwidth.nwrites.read()) nwrites = (yield from dut.bandwidth.nwrites.read())
self.assertEqual(nreads, 0) self.assertEqual(nreads, 0)
self.assertEqual(nwrites, 0) self.assertEqual(nwrites, 0)
@ -106,7 +106,7 @@ class TestBandwidth(unittest.TestCase):
# Update register values # Update register values
yield from dut.bandwidth.update.write(1) yield from dut.bandwidth.update.write(1)
nreads = (yield from dut.bandwidth.nreads.read()) nreads = (yield from dut.bandwidth.nreads.read())
nwrites = (yield from dut.bandwidth.nwrites.read()) nwrites = (yield from dut.bandwidth.nwrites.read())
self.assertNotEqual((nreads, nwrites), (0, 0)) self.assertNotEqual((nreads, nwrites), (0, 0))
@ -128,7 +128,7 @@ class TestBandwidth(unittest.TestCase):
yield yield
yield from dut.bandwidth.update.write(1) yield from dut.bandwidth.update.write(1)
yield yield
results["nreads"] = (yield from dut.bandwidth.nreads.read()) results["nreads"] = (yield from dut.bandwidth.nreads.read())
results["nwrites"] = (yield from dut.bandwidth.nwrites.read()) results["nwrites"] = (yield from dut.bandwidth.nwrites.read())
dut = BandwidthDUT(period_bits=8) dut = BandwidthDUT(period_bits=8)
@ -156,7 +156,7 @@ class TestBandwidth(unittest.TestCase):
dut = BandwidthDUT(period_bits=8) dut = BandwidthDUT(period_bits=8)
cmd_driver = CommandDriver(dut.cmd) cmd_driver = CommandDriver(dut.cmd)
commands = ["read", "write", "activate", "precharge", "refresh"] commands = ["read", "write", "activate", "precharge", "refresh"]
generators = [ generators = [
main_generator(dut), main_generator(dut),
cmd_driver.random_generator(commands=commands), cmd_driver.random_generator(commands=commands),
@ -166,7 +166,7 @@ class TestBandwidth(unittest.TestCase):
self.assertEqual(results["nreads"], cmd_driver.cmd_counts["read"]) self.assertEqual(results["nreads"], cmd_driver.cmd_counts["read"])
def test_correct_period_length(self): def test_correct_period_length(self):
# Verify that period length is correct by measuring time betwee CSR changes. # Verify that period length is correct by measuring time between CSR changes.
period_bits = 5 period_bits = 5
period = 2**period_bits period = 2**period_bits