test: add downconverter_tb and some fixes

litedram/frontend/crossbar.py

@@ -85,10 +85,10 @@ class _LiteDRAMDownConverter(Module):
         fsm.act("IDLE",
             counter_reset.eq(1),
             If(port_from.cmd.valid,
-                NextState("ADAPT")
+                NextState("CONVERT")
             )
         )
-        fsm.act("ADAPT",
+        fsm.act("CONVERT",
             port_to.cmd.valid.eq(1),
             port_to.cmd.we.eq(port_from.cmd.we),
             port_to.cmd.adr.eq(port_from.cmd.adr*ratio + counter),
@@ -102,7 +102,7 @@ class _LiteDRAMDownConverter(Module):
         )
 
         wdata_converter = stream.StrideConverter(port_from.wdata.description,
-                                                 port_to.wdata.descritpion)
+                                                 port_to.wdata.description)
         self.submodules += wdata_converter
         self.comb += [
             port_from.wdata.connect(wdata_converter.sink),
@@ -178,7 +178,7 @@ class _LiteDRAMUpConverter(Module):
         )
 
         wdata_converter = stream.StrideConverter(port_from.wdata.description,
-                                                 port_to.wdata.descritpion)
+                                                 port_to.wdata.description)
         self.submodules += wdata_converter
         self.comb += [
             port_from.wdata.connect(wdata_converter.sink),
@@ -202,10 +202,15 @@ class LiteDRAMConverter(Module):
         if port_from.dw > port_to.dw:
             converter = _LiteDRAMDownConverter(port_from, port_to)
             self.submodules += converter
-        elif port_from.dw < port.to.dw:
+        elif port_from.dw < port_to.dw:
             converter = _LiteDRAMUpConverter(port_from, port_to)
             self.submodules += converter
-
+        else:
+            self.comb += [
+                port_from.cmd.connect(port_to.cmd),
+                port_from.wdata.connect(port_to.wdata),
+                port_to.rdata.connect(port_from.rdata)
+            ]
 
 class LiteDRAMCrossbar(Module):
     def __init__(self, controller, cba_shift):

test/Makefile

@@ -9,4 +9,7 @@ bist_tb:
 bist_async_tb:
 	$(CMD) bist_async_tb.py
 
-all: bist_tb bist_async_tb
+downconverter_tb:
+	$(CMD) downconverter_tb.py
+
+all: bist_tb bist_async_tb downconverter_tb

test/common.py

@@ -45,9 +45,11 @@ class DRAMMemory:
                 yield dram_port.wdata.ready.eq(0)
                 yield
                 pending = 0
-            elif (yield dram_port.cmd.valid):
-                pending = yield dram_port.cmd.we
-                address = (yield dram_port.cmd.adr)
                 yield
+            elif (yield dram_port.cmd.valid):
+                pending = (yield dram_port.cmd.we)
+                address = (yield dram_port.cmd.adr)
                 yield dram_port.cmd.ready.eq(1)
                 yield
+                yield dram_port.cmd.ready.eq(0)
+            yield

test/downconverter_tb.py

@@ -0,0 +1,41 @@
+from litex.gen import *
+
+from litex.soc.interconnect.stream import *
+
+from litedram.common import LiteDRAMPort
+from litedram.frontend.crossbar import LiteDRAMConverter
+
+from test.common import DRAMMemory
+
+class TB(Module):
+    def __init__(self):
+        self.user_port = LiteDRAMPort(aw=32, dw=64)
+        self.internal_port = LiteDRAMPort(aw=32, dw=32)
+        self.submodules.converter = LiteDRAMConverter(self.user_port, self.internal_port)
+        self.memory = DRAMMemory(32, 128)
+
+def main_generator(dut):
+    for i in range(8):
+        yield
+    # write
+    for i in range(8):
+        yield dut.user_port.cmd.valid.eq(1)
+        yield dut.user_port.cmd.we.eq(1)
+        yield dut.user_port.cmd.adr.eq(i)
+        yield dut.user_port.wdata.valid.eq(1)
+        yield dut.user_port.wdata.data.eq(0x0123456789abcdef)
+        yield
+        while (yield dut.user_port.cmd.ready) == 0:
+            yield
+        while (yield dut.user_port.wdata.ready) == 0:
+            yield
+        yield
+
+if __name__ == "__main__":
+    tb = TB()
+    generators = {
+        "sys" :   [main_generator(tb),
+                   tb.memory.write_generator(tb.internal_port)]
+    }
+    clocks = {"sys": 10}
+    run_simulation(tb, generators, clocks, vcd_name="sim.vcd")