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frontend/adapter: simplify LiteDRAMNativePortDownConverter.
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commit
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1 changed files with 14 additions and 24 deletions
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@ -75,20 +75,11 @@ class LiteDRAMNativePortDownConverter(Module):
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ratio = port_from.data_width//port_to.data_width
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mode = port_from.mode
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counter = Signal(max=ratio)
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counter_reset = Signal()
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counter_ce = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 1)
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)
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count = Signal(max=ratio)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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counter_reset.eq(1),
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NextValue(count, 0),
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If(port_from.cmd.valid,
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NextState("CONVERT")
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)
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@ -96,30 +87,29 @@ class LiteDRAMNativePortDownConverter(Module):
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fsm.act("CONVERT",
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port_to.cmd.valid.eq(1),
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port_to.cmd.we.eq(port_from.cmd.we),
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port_to.cmd.addr.eq(port_from.cmd.addr*ratio + counter),
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port_to.cmd.addr.eq(port_from.cmd.addr*ratio + count),
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If(port_to.cmd.ready,
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counter_ce.eq(1),
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If(counter == ratio - 1,
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NextValue(count, count + 1),
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If(count == (ratio - 1),
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port_from.cmd.ready.eq(1),
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NextState("IDLE")
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)
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)
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)
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if mode == "write" or mode == "both":
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if mode in ["write", "both"]:
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wdata_converter = stream.StrideConverter(
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port_from.wdata.description,
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port_to.wdata.description,
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reverse=reverse)
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description_from = port_from.wdata.description,
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description_to = port_to.wdata.description,
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reverse = reverse)
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self.submodules += wdata_converter
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self.submodules += stream.Pipeline(
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port_from.wdata, wdata_converter, port_to.wdata)
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self.submodules += stream.Pipeline(port_from.wdata, wdata_converter, port_to.wdata)
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if mode == "read" or mode == "both":
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if mode in ["read", "both"]:
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rdata_converter = stream.StrideConverter(
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port_to.rdata.description,
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port_from.rdata.description,
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reverse=reverse)
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description_from = port_to.rdata.description,
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description_to = port_from.rdata.description,
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reverse = reverse)
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self.submodules += rdata_converter
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self.submodules += stream.Pipeline(
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port_to.rdata, rdata_converter, port_from.rdata)
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