test/reference: update
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@ -25,6 +25,7 @@
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#define SDRAM_PHY_RDPHASE 0
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#define SDRAM_PHY_WRPHASE 1
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#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
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#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
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#define SDRAM_PHY_READ_LEVELING_CAPABLE
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#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
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#define SDRAM_PHY_DELAYS 32
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@ -26,6 +26,7 @@
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#define SDRAM_PHY_WRPHASE 2
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#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
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#define SDRAM_PHY_WRITE_LEVELING_REINIT
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#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
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#define SDRAM_PHY_READ_LEVELING_CAPABLE
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#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
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#define SDRAM_PHY_DELAYS 512
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