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phy/usddrphy: make clk/cmd odelaye3s configurable 

Required on some DDR4 boards of optimal write-leveling calibration
This commit is contained in:
Florent Kermarrec 2019-02-13 12:06:17 +01:00
parent d89b17177a
commit e0224f458c
1 changed files with 27 additions and 12 deletions
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39
litedram/phy/usddrphy.py
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@ -78,6 +78,9 @@ class USDDRPHY(Module, AutoCSR):
self._wlevel_en = CSRStorage() self._wlevel_en = CSRStorage()
self._wlevel_strobe = CSR() self._wlevel_strobe = CSR()
self._cdly_rst = CSR()
self._cdly_inc = CSR()
self._dly_sel = CSRStorage(databits//8) self._dly_sel = CSRStorage(databits//8)
self._rdly_dq_rst = CSR() self._rdly_dq_rst = CSR()
@ -137,10 +140,13 @@ class USDDRPHY(Module, AutoCSR):
), ),
Instance("ODELAYE3", Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(), i_CLK=ClockSignal(),
i_RST=0, i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_EN_VTC=1, i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=clk_o_nodelay, o_DATAOUT=clk_o_delayed i_ODATAIN=clk_o_nodelay, o_DATAOUT=clk_o_delayed
), ),
Instance("OBUFDS", Instance("OBUFDS",
@ -168,10 +174,13 @@ class USDDRPHY(Module, AutoCSR):
), ),
Instance("ODELAYE3", Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(), i_CLK=ClockSignal(),
i_RST=0, i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_EN_VTC=1, i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=a_o_nodelay, o_DATAOUT=pads.a[i] i_ODATAIN=a_o_nodelay, o_DATAOUT=pads.a[i]
) )
] ]
@ -199,10 +208,13 @@ class USDDRPHY(Module, AutoCSR):
), ),
Instance("ODELAYE3", Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(), i_CLK=ClockSignal(),
i_RST=0, i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_EN_VTC=1, i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=ba_o_nodelay, o_DATAOUT=pads_ba[i] i_ODATAIN=ba_o_nodelay, o_DATAOUT=pads_ba[i]
) )
] ]
@ -231,10 +243,13 @@ class USDDRPHY(Module, AutoCSR):
), ),
Instance("ODELAYE3", Instance("ODELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6, p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=iodelay_clk_freq/1e6,
p_DELAY_FORMAT="TIME", p_DELAY_TYPE="FIXED", p_DELAY_VALUE=0, p_DELAY_FORMAT="TIME", p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal(), i_CLK=ClockSignal(),
i_RST=0, i_INC=1, i_EN_VTC=self._en_vtc.storage,
i_EN_VTC=1, i_RST=self._cdly_rst.re,
i_CE=self._cdly_inc.re,
i_ODATAIN=x_o_nodelay, o_DATAOUT=getattr(pads, name) i_ODATAIN=x_o_nodelay, o_DATAOUT=getattr(pads, name)
) )
] ]