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phy/ecp5ddrphy: improve presentation/readability

This commit is contained in:
Florent Kermarrec 2020-01-25 15:30:00 +01:00
parent bb1b431184
commit e0966e2ed3
1 changed files with 192 additions and 198 deletions
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46
litedram/phy/ecp5ddrphy.py
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@ -1,5 +1,5 @@
# This file is Copyright (c) 2019 David Shah <dave@ds0.me> # This file is Copyright (c) 2019 David Shah <dave@ds0.me>
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD # License: BSD
# 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5 # 1:2 frequency-ratio DDR3 PHY for Lattice's ECP5
@ -141,8 +141,7 @@ class ECP5DDRPHY(Module, AutoCSR):
# Clock ------------------------------------------------------------------------------------ # Clock ------------------------------------------------------------------------------------
for i in range(len(pads.clk_p)): for i in range(len(pads.clk_p)):
sd_clk_se = Signal() sd_clk_se = Signal()
self.specials += [ self.specials += Instance("ODDRX2F",
Instance("ODDRX2F",
i_D0 = 0, i_D0 = 0,
i_D1 = 1, i_D1 = 1,
i_D2 = 0, i_D2 = 0,
@ -151,13 +150,11 @@ class ECP5DDRPHY(Module, AutoCSR):
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys2x"),
o_Q = pads.clk_p[i] o_Q = pads.clk_p[i]
), )
]
# Addresses and Commands ------------------------------------------------------------------- # Addresses and Commands -------------------------------------------------------------------
for i in range(addressbits): for i in range(addressbits):
self.specials += \ self.specials += Instance("ODDRX2F",
Instance("ODDRX2F",
i_D0 = dfi.phases[0].address[i], i_D0 = dfi.phases[0].address[i],
i_D1 = dfi.phases[0].address[i], i_D1 = dfi.phases[0].address[i],
i_D2 = dfi.phases[1].address[i], i_D2 = dfi.phases[1].address[i],
@ -168,8 +165,7 @@ class ECP5DDRPHY(Module, AutoCSR):
o_Q = pads.a[i] o_Q = pads.a[i]
) )
for i in range(bankbits): for i in range(bankbits):
self.specials += \ self.specials += Instance("ODDRX2F",
Instance("ODDRX2F",
i_D0 = dfi.phases[0].bank[i], i_D0 = dfi.phases[0].bank[i],
i_D1 = dfi.phases[0].bank[i], i_D1 = dfi.phases[0].bank[i],
i_D2 = dfi.phases[1].bank[i], i_D2 = dfi.phases[1].bank[i],
@ -186,8 +182,7 @@ class ECP5DDRPHY(Module, AutoCSR):
controls.append("cs_n") controls.append("cs_n")
for name in controls: for name in controls:
for i in range(len(getattr(pads, name))): for i in range(len(getattr(pads, name))):
self.specials += \ self.specials += Instance("ODDRX2F",
Instance("ODDRX2F",
i_D0 = getattr(dfi.phases[0], name)[i], i_D0 = getattr(dfi.phases[0], name)[i],
i_D1 = getattr(dfi.phases[0], name)[i], i_D1 = getattr(dfi.phases[0], name)[i],
i_D2 = getattr(dfi.phases[1], name)[i], i_D2 = getattr(dfi.phases[1], name)[i],
@ -293,8 +288,7 @@ class ECP5DDRPHY(Module, AutoCSR):
).Else( ).Else(
dm_o_data_muxed.eq(dm_o_data[:4]) dm_o_data_muxed.eq(dm_o_data[:4])
) )
self.specials += \ self.specials += Instance("ODDRX2DQA",
Instance("ODDRX2DQA",
i_D0 = dm_o_data_muxed[0], i_D0 = dm_o_data_muxed[0],
i_D1 = dm_o_data_muxed[1], i_D1 = dm_o_data_muxed[1],
i_D2 = dm_o_data_muxed[2], i_D2 = dm_o_data_muxed[2],
@ -308,7 +302,7 @@ class ECP5DDRPHY(Module, AutoCSR):
dqs = Signal() dqs = Signal()
dqs_oe_n = Signal() dqs_oe_n = Signal()
self.specials += \ self.specials += [
Instance("ODDRX2DQSB", Instance("ODDRX2DQSB",
i_D0 = dqs_serdes_pattern[0], i_D0 = dqs_serdes_pattern[0],
i_D1 = dqs_serdes_pattern[1], i_D1 = dqs_serdes_pattern[1],
@ -319,8 +313,7 @@ class ECP5DDRPHY(Module, AutoCSR):
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
o_Q = dqs o_Q = dqs
) ),
self.specials += \
Instance("TSHX2DQSA", Instance("TSHX2DQSA",
i_T0 = ~(oe_dqs|dqs_postamble), i_T0 = ~(oe_dqs|dqs_postamble),
i_T1 = ~(oe_dqs|dqs_preamble), i_T1 = ~(oe_dqs|dqs_preamble),
@ -329,8 +322,9 @@ class ECP5DDRPHY(Module, AutoCSR):
i_DQSW = dqsw, i_DQSW = dqsw,
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys2x"),
o_Q = dqs_oe_n, o_Q = dqs_oe_n,
) ),
self.specials += Tristate(pads.dqs_p[i], dqs, ~dqs_oe_n, dqs_i) Tristate(pads.dqs_p[i], dqs, ~dqs_oe_n, dqs_i)
]
for j in range(8*i, 8*(i+1)): for j in range(8*i, 8*(i+1)):
dq_o = Signal() dq_o = Signal()
@ -354,7 +348,7 @@ class ECP5DDRPHY(Module, AutoCSR):
).Else( ).Else(
dq_o_data_muxed.eq(dq_o_data[:4]) dq_o_data_muxed.eq(dq_o_data[:4])
) )
self.specials += \ self.specials += [
Instance("ODDRX2DQA", Instance("ODDRX2DQA",
i_D0 = dq_o_data_muxed[0], i_D0 = dq_o_data_muxed[0],
i_D1 = dq_o_data_muxed[1], i_D1 = dq_o_data_muxed[1],
@ -365,8 +359,7 @@ class ECP5DDRPHY(Module, AutoCSR):
i_ECLK = ClockSignal("sys2x"), i_ECLK = ClockSignal("sys2x"),
i_SCLK = ClockSignal(), i_SCLK = ClockSignal(),
o_Q = dq_o o_Q = dq_o
) ),
self.specials += \
Instance("DELAYF", Instance("DELAYF",
i_A = dq_i, i_A = dq_i,
i_LOADN = 1, i_LOADN = 1,
@ -374,8 +367,7 @@ class ECP5DDRPHY(Module, AutoCSR):
i_DIRECTION = 0, i_DIRECTION = 0,
o_Z = dq_i_delayed, o_Z = dq_i_delayed,
p_DEL_MODE = "DQS_ALIGNED_X2" p_DEL_MODE = "DQS_ALIGNED_X2"
) ),
self.specials += \
Instance("IDDRX2DQA", Instance("IDDRX2DQA",
i_D = dq_i_delayed, i_D = dq_i_delayed,
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys2x"),
@ -393,6 +385,7 @@ class ECP5DDRPHY(Module, AutoCSR):
o_Q2 = dq_i_data[2], o_Q2 = dq_i_data[2],
o_Q3 = dq_i_data[3], o_Q3 = dq_i_data[3],
) )
]
dq_bitslip = BitSlip(4) dq_bitslip = BitSlip(4)
self.comb += dq_bitslip.i.eq(dq_i_data) self.comb += dq_bitslip.i.eq(dq_i_data)
self.sync += \ self.sync += \
@ -412,7 +405,7 @@ class ECP5DDRPHY(Module, AutoCSR):
dfi.phases[1].rddata[0*databits+j].eq(dq_bitslip.o[0]), dfi.phases[1].rddata[1*databits+j].eq(dq_bitslip.o[1]), dfi.phases[1].rddata[0*databits+j].eq(dq_bitslip.o[0]), dfi.phases[1].rddata[1*databits+j].eq(dq_bitslip.o[1]),
dfi.phases[1].rddata[2*databits+j].eq(dq_bitslip.o[2]), dfi.phases[1].rddata[3*databits+j].eq(dq_bitslip.o[3]), dfi.phases[1].rddata[2*databits+j].eq(dq_bitslip.o[2]), dfi.phases[1].rddata[3*databits+j].eq(dq_bitslip.o[3]),
] ]
self.specials += \ self.specials += [
Instance("TSHX2DQA", Instance("TSHX2DQA",
i_T0 = ~oe_dq, i_T0 = ~oe_dq,
i_T1 = ~oe_dq, i_T1 = ~oe_dq,
@ -421,8 +414,9 @@ class ECP5DDRPHY(Module, AutoCSR):
i_DQSW270 = dqsw270, i_DQSW270 = dqsw270,
i_RST = ResetSignal("sys2x"), i_RST = ResetSignal("sys2x"),
o_Q = dq_oe_n, o_Q = dq_oe_n,
) ),
self.specials += Tristate(pads.dq[j], dq_o, ~dq_oe_n, dq_i) Tristate(pads.dq[j], dq_o, ~dq_oe_n, dq_i)
]
# Flow control ----------------------------------------------------------------------------- # Flow control -----------------------------------------------------------------------------
# #