phy/ecp5ddrphy: cosmetics.
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@ -143,7 +143,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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for pads_group in range(len(pads.groups)):
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pads.sel_group(pads_group)
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# Clock ------------------------------------------------------------------------------------
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# Clock --------------------------------------------------------------------------------
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for i in range(len(pads.clk_p)):
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sd_clk_se = Signal()
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self.specials += Instance("ODDRX2F",
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@ -157,7 +157,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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o_Q = pads.clk_p[i]
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)
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# Addresses and Commands -------------------------------------------------------------------
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# Addresses and Commands ---------------------------------------------------------------
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for i in range(addressbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys2x"),
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@ -281,10 +281,15 @@ class ECP5DDRPHY(Module, AutoCSR):
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dm_o_data_d = Signal(8)
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dm_o_data_muxed = Signal(4)
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self.comb += dm_o_data.eq(Cat(
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dfi.phases[0].wrdata_mask[0*databits//8+i], dfi.phases[0].wrdata_mask[1*databits//8+i],
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dfi.phases[0].wrdata_mask[2*databits//8+i], dfi.phases[0].wrdata_mask[3*databits//8+i],
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dfi.phases[1].wrdata_mask[0*databits//8+i], dfi.phases[1].wrdata_mask[1*databits//8+i],
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dfi.phases[1].wrdata_mask[2*databits//8+i], dfi.phases[1].wrdata_mask[3*databits//8+i]),
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dfi.phases[0].wrdata_mask[0*databits//8+i],
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dfi.phases[0].wrdata_mask[1*databits//8+i],
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dfi.phases[0].wrdata_mask[2*databits//8+i],
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dfi.phases[0].wrdata_mask[3*databits//8+i],
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dfi.phases[1].wrdata_mask[0*databits//8+i],
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dfi.phases[1].wrdata_mask[1*databits//8+i],
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dfi.phases[1].wrdata_mask[2*databits//8+i],
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dfi.phases[1].wrdata_mask[3*databits//8+i]),
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)
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self.sync += dm_o_data_d.eq(dm_o_data)
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self.sync += \
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@ -341,10 +346,15 @@ class ECP5DDRPHY(Module, AutoCSR):
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dq_o_data_d = Signal(8)
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dq_o_data_muxed = Signal(4)
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self.comb += dq_o_data.eq(Cat(
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dfi.phases[0].wrdata[0*databits+j], dfi.phases[0].wrdata[1*databits+j],
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dfi.phases[0].wrdata[2*databits+j], dfi.phases[0].wrdata[3*databits+j],
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dfi.phases[1].wrdata[0*databits+j], dfi.phases[1].wrdata[1*databits+j],
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dfi.phases[1].wrdata[2*databits+j], dfi.phases[1].wrdata[3*databits+j])
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dfi.phases[0].wrdata[0*databits+j],
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dfi.phases[0].wrdata[1*databits+j],
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dfi.phases[0].wrdata[2*databits+j],
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dfi.phases[0].wrdata[3*databits+j],
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dfi.phases[1].wrdata[0*databits+j],
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dfi.phases[1].wrdata[1*databits+j],
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dfi.phases[1].wrdata[2*databits+j],
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dfi.phases[1].wrdata[3*databits+j])
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)
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self.sync += dq_o_data_d.eq(dq_o_data)
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self.sync += \
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