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phy/s7ddrphy and usddrphy: add cmd_latency parameter 

On some boards, we need to delay command to have a optimal write_leveling window,
cmd_latency can be use to delay write data so that cwl is ensured.
This commit is contained in:
Florent Kermarrec 2019-02-19 18:00:23 +01:00
parent fd3e9afbcd
commit ea6b841dfe
2 changed files with 6 additions and 5 deletions
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6
litedram/phy/s7ddrphy.py
View File

@ -42,9 +42,8 @@ def get_sys_phases(nphases, sys_latency, cas_latency):
cmd_phase = (dat_phase - 1)%nphases cmd_phase = (dat_phase - 1)%nphases
return cmd_phase, dat_phase return cmd_phase, dat_phase
class S7DDRPHY(Module, AutoCSR): class S7DDRPHY(Module, AutoCSR):
def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=100e6, iodelay_clk_freq=200e6): def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0):
assert not (memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2 assert not (memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2
tck = 2/(2*nphases*sys_clk_freq) tck = 2/(2*nphases*sys_clk_freq)
addressbits = len(pads.a) addressbits = len(pads.a)
@ -85,6 +84,7 @@ class S7DDRPHY(Module, AutoCSR):
# compute phy settings # compute phy settings
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
@ -99,7 +99,7 @@ class S7DDRPHY(Module, AutoCSR):
rdcmdphase=rdcmdphase, rdcmdphase=rdcmdphase,
wrcmdphase=wrcmdphase, wrcmdphase=wrcmdphase,
cl=cl, cl=cl,
cwl=cwl, cwl=cwl - cmd_latency,
read_latency=2 + cl_sys_latency + 2 + 3, read_latency=2 + cl_sys_latency + 2 + 3,
write_latency=cwl_sys_latency write_latency=cwl_sys_latency
) )

5
litedram/phy/usddrphy.py
View File

@ -58,7 +58,7 @@ class DDR4DFIMux(Module):
class USDDRPHY(Module, AutoCSR): class USDDRPHY(Module, AutoCSR):
def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6, iodelay_clk_freq=200e6): def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0):
tck = 2/(2*4*sys_clk_freq) tck = 2/(2*4*sys_clk_freq)
addressbits = len(pads.a) addressbits = len(pads.a)
if memtype == "DDR4": if memtype == "DDR4":
@ -95,6 +95,7 @@ class USDDRPHY(Module, AutoCSR):
# compute phy settings # compute phy settings
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cwl = cwl + cmd_latency
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
@ -110,7 +111,7 @@ class USDDRPHY(Module, AutoCSR):
rdcmdphase=rdcmdphase, rdcmdphase=rdcmdphase,
wrcmdphase=wrcmdphase, wrcmdphase=wrcmdphase,
cl=cl, cl=cl,
cwl=cwl, cwl=cwl - cmd_latency,
read_latency=2 + cl_sys_latency + 1 + 3, read_latency=2 + cl_sys_latency + 1 + 3,
write_latency=cwl_sys_latency write_latency=cwl_sys_latency
) )