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fix CAS to CAS timings (needs to account for multiple banks)

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This commit is contained in:
2018-07-31 01:57:55 -04:00
parent f0f5e6036b
commit eb3f4a05f6
2 changed files with 16 additions and 15 deletions
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16
litedram/core/bankmachine.py
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@ -31,6 +31,7 @@ class BankMachine(Module):
self.req = req = Record(cmd_layout(aw))
self.refresh_req = Signal()
self.refresh_gnt = Signal()
self.cas_allowed = cas_allowed = Signal()
self.activate_allowed = activate_allowed = Signal()
a = settings.geom.addressbits
ba = settings.geom.bankbits
@ -67,20 +68,6 @@ class BankMachine(Module):
openrow.eq(slicer.row(cmd_buffer.source.adr))
)
# CAS to CAS
cas = Signal()
cas_allowed = Signal(reset=1)
tccd = settings.timing.tCCD
if tccd is not None:
cas_count = Signal(max=tccd+1)
self.sync += \
If(cas,
cas_count.eq(tccd-1)
).Elif(~cas_allowed,
cas_count.eq(cas_count-1)
)
self.comb += cas_allowed.eq(cas_count == 0)
# Address generation
sel_row_adr = Signal()
self.comb += [
@ -108,7 +95,6 @@ class BankMachine(Module):
If(has_openrow,
If(hit,
If(cas_allowed,
cas.eq(1),
# Note: write-to-read specification is enforced by
# multiplexer
cmd.valid.eq(1),

15
litedram/core/multiplexer.py
View file

@ -165,6 +165,21 @@ class Multiplexer(Module, AutoCSR):
self.comb += activate_allowed.eq(trrd_allowed & tfaw_allowed)
self.comb += [bm.activate_allowed.eq(activate_allowed) for bm in bank_machines]
# CAS to CAS
cas = choose_req.cmd.valid & choose_req.cmd.ready & (choose_req.cmd.is_read | choose_req.cmd.is_write)
cas_allowed = Signal(reset=1)
tccd = settings.timing.tCCD
if tccd is not None:
cas_count = Signal(max=tccd+1)
self.sync += \
If(cas,
cas_count.eq(tccd-1)
).Elif(~cas_allowed,
cas_count.eq(cas_count-1)
)
self.comb += cas_allowed.eq(cas_count == 0)
self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
# Read/write turnaround
read_available = Signal()
write_available = Signal()