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phy/ecp5/s7/us: allow user to provide cl/cwl instead of default values. 

One some hardware, forcing cl or/and cwl to non-default values can provide
better results.
This commit is contained in:
Florent Kermarrec 2021-01-04 11:40:34 +01:00
parent d4c5c7cef8
commit ec1f34f5f9
3 changed files with 11 additions and 4 deletions
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5
litedram/phy/ecp5ddrphy.py
View File

@ -112,7 +112,7 @@ class ECP5DDRPHYInit(Module):
# Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
class ECP5DDRPHY(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq=100e6, dm_remapping={}):
def __init__(self, pads, sys_clk_freq=100e6, cl=None, cwl=None, dm_remapping={}):
pads = PHYPadsCombiner(pads)
memtype = "DDR3"
tck = 2/(2*2*sys_clk_freq)
@ -127,7 +127,8 @@ class ECP5DDRPHY(Module, AutoCSR):
self.submodules.init = ECP5DDRPHYInit()
# Parameters -------------------------------------------------------------------------------
cl, cwl = get_default_cl_cwl(memtype, tck)
cl = get_default_cl( memtype, tck) if cl is None else cl
cwl = get_default_cwl(memtype, tck) if cwl is None else cwl
cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl)

5
litedram/phy/s7ddrphy.py
View File

@ -29,6 +29,8 @@ class S7DDRPHY(Module, AutoCSR):
nphases = 4,
sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6,
cl = None,
cwl = None,
cmd_latency = 0,
cmd_delay = None):
assert not (memtype == "DDR3" and nphases == 2)
@ -50,7 +52,8 @@ class S7DDRPHY(Module, AutoCSR):
}
half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
cl, cwl = get_default_cl_cwl(memtype, tck)
cl = get_default_cl( memtype, tck) if cl is None else cl
cwl = get_default_cwl(memtype, tck) if cwl is None else cwl
cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl + cmd_latency)

5
litedram/phy/usddrphy.py
View File

@ -28,6 +28,8 @@ class USDDRPHY(Module, AutoCSR):
memtype = "DDR3",
sys_clk_freq = 100e6,
iodelay_clk_freq = 200e6,
cl = None,
cwl = None,
cmd_latency = 0,
cmd_delay = None,
is_rdimm = False):
@ -49,7 +51,8 @@ class USDDRPHY(Module, AutoCSR):
if phytype == "USDDRPHY": assert iodelay_clk_freq >= 200e6
if phytype == "USPDDRPHY": assert iodelay_clk_freq >= 300e6
cl, cwl = get_default_cl_cwl(memtype, tck)
cl = get_default_cl( memtype, tck) if cl is None else cl
cwl = get_default_cwl(memtype, tck) if cwl is None else cwl
cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl + cmd_latency)