lpddr4: implement ZQC through MPC and include it in init sequence
We do not yet support ZQC during operation (after init sequence) as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between, which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
This commit is contained in:
Jędrzej Boczar
parent
055e2dc597
commit
ee9c2b4cf7
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@ -554,11 +554,16 @@ def get_lpddr4_phy_init_sequence(phy_settings, timing_settings):
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ba = 0
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return ("Load More Register {}".format(ma), a, ba, cmds["MODE_REGISTER"], 200)
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from litedram.phy.lpddr4phy import DFIPhaseAdapter
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zqc_start = DFIPhaseAdapter.MPC["ZQC-START"]
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zqc_latch = DFIPhaseAdapter.MPC["ZQC-LATCH"]
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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*[cmd_mr(ma) for ma in sorted(mr.keys())],
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# TODO: ZQ calibration
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("ZQ Calibration start", zqc_start, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 1000), # > tZQCAL=1us
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("ZQ Calibration latch", zqc_latch, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200), # > tZQLAT=max(8ck, 30ns)
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]
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return init_sequence, mr
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@ -974,7 +974,10 @@ class MT53E256M16D1(SDRAMModule):
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nrows = 32768
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ncols = 1024
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technology_timings = _TechnologyTimings(tREFI=32e6/8192, tWTR=(8, 10), tCCD=(8, None), tRRD=(4, 10), tZQCS=None) # TODO: tZQCS
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# TODO: tZQCS - performing ZQC during runtime will require modifying Refresher, as ZQC has to be done in 2 phases
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# 1. ZQCAL START is issued 2. ZQCAL LATCH updates the values, the time START->LATCH tZQCAL=1us, so we cannot block
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# the controller during this time, after ZQCAL LATCH we have to wait tZQLAT=max(8ck, 30ns)
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technology_timings = _TechnologyTimings(tREFI=32e6/8192, tWTR=(8, 10), tCCD=(8, None), tRRD=(4, 10), tZQCS=None)
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speedgrade_timings = {
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"1866": _SpeedgradeTimings(tRP=(3, 21), tRCD=(4, 18), tWR=(4, 18), tRFC=180, tFAW=40, tRAS=(3, 42)), # TODO: tRAS_max
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}
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@ -384,6 +384,22 @@ class DFIPhaseAdapter(Module):
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# Then most "big commands" consist of 2 "small commands" (e.g. ACTIVATE-1, ACTIVATE-2).
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# If a command uses 1 "small command", then it shall go as cmd2 so that all command
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# timings can be counted from the same moment (cycle of cmd2 CS low).
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# MPC (multipurpose command) can be used to perform different actions
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# We use ZQC with BA=0 to issue MPC, where OP[6:0] = A[6:0]
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MPC = {
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"NOP": 0b0000000, # only OP[6] must be 0
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"READ-FIFO": 0b1000001,
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"READ-DQ-CAL": 0b1000011,
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# RFU: 0b1000101
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"WRITE-FIFO": 0b1000111,
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# RFU: 0b1001001
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"START-DQS-OSC": 0b1001011,
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"STOP-DQS-OSC": 0b1001101,
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"ZQC-START": 0b1001111,
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"ZQC-LATCH": 0b1010001,
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}
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def __init__(self, dfi_phase):
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# CS/CA values for 4 SDR cycles
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self.cs = Signal(4)
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@ -426,11 +442,7 @@ class DFIPhaseAdapter(Module):
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_cmd["WR"]: cmds("WRITE-1", "CAS-2"), # TODO: masked write
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_cmd["PRE"]: cmds("DESELECT", "PRECHARGE"),
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_cmd["REF"]: cmds("DESELECT", "REFRESH"),
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# TODO: ZQC init/short/long? start/latch?
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# _cmd["ZQC"]: [
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# *cmds("DESELECT", "MPC"),
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# self.cmd2.mpc.eq(0b1001111),
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# ],
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_cmd["ZQC"]: cmds("DESELECT", "MPC"),
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_cmd["MRS"]: cmds("MRW-1", "MRW-2"),
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"default": cmds("DESELECT", "DESELECT", valid=0),
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})
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@ -462,7 +474,6 @@ class Command(Module):
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def __init__(self, dfi_phase):
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self.cs = Signal(2)
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self.ca = Array([Signal(6), Signal(6)]) # CS high, CS low
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self.mpc = Signal(7) # special OP values for multipurpose command
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self.dfi = dfi_phase
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def set(self, cmd):
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@ -487,8 +498,7 @@ class Command(Module):
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"R(\d+)": lambda i: self.dfi.address[i], # row
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"C(\d+)": lambda i: self.dfi.address[i], # column
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"MA(\d+)": lambda i: self.dfi.address[8+i], # mode register address
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# mode register value, or op code for MPC
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"OP(\d+)": lambda i: self.mpc[i] if is_mpc else self.dfi.address[i],
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"OP(\d+)": lambda i: self.dfi.address[i], # mode register value, or operand for MPC
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}
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for pattern, value in rules.items():
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m = re.match(pattern, bit)
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@ -506,22 +506,25 @@ class TestLPDDR4(unittest.TestCase):
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refresh_ab = dict(cs_n=0, cas_n=0, ras_n=0, we_n=1, bank=0b100, address=0b10000000000)
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precharge = dict(cs_n=0, cas_n=1, ras_n=0, we_n=0, bank=0b011, address=0)
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mrw = dict(cs_n=0, cas_n=0, ras_n=0, we_n=0, bank=0, address=(0b110011 << 8) | 0b10101010) # 6-bit address | 8-bit op code
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zqc_start = dict(cs_n=0, cas_n=1, ras_n=1, we_n=0, bank=0, address=0b1001111) # MPC with ZQCAL START operand
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zqc_latch = dict(cs_n=0, cas_n=1, ras_n=1, we_n=0, bank=0, address=0b1010001) # MPC with ZQCAL LATCH operand
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self.run_test(SimulationPHY(),
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dfi_sequence = [
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{0: read, 4: write_ap},
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{0: activate, 4: refresh_ab},
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{0: precharge, 4: mrw},
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{0: zqc_start, 4: zqc_latch},
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],
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pad_checkers = {"sys8x_90": {
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# note that refresh and precharge have a single command so these go as cmd2
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# rd wr act ref pre mrw
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'cs': latency + '1010'+'1010' + '1010'+'0010' + '0010'+'1010',
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'ca0': latency + '0100'+'0100' + '1011'+'0000' + '0001'+'0100',
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'ca1': latency + '1010'+'0110' + '0110'+'0000' + '0001'+'1111',
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'ca2': latency + '0101'+'1100' + '0010'+'0001' + '0000'+'1010',
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'ca3': latency + '0x01'+'0x00' + '1110'+'001x' + '000x'+'0001',
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'ca4': latency + '0110'+'0010' + '1010'+'000x' + '001x'+'0110',
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'ca5': latency + '0010'+'0100' + '1001'+'001x' + '000x'+'1101',
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# rd wr act ref pre mrw zqcs zqcl
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'cs': latency + '1010'+'1010' + '1010'+'0010' + '0010'+'1010' + '0010'+'0010',
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'ca0': latency + '0100'+'0100' + '1011'+'0000' + '0001'+'0100' + '0001'+'0001',
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'ca1': latency + '1010'+'0110' + '0110'+'0000' + '0001'+'1111' + '0001'+'0000',
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'ca2': latency + '0101'+'1100' + '0010'+'0001' + '0000'+'1010' + '0001'+'0000',
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'ca3': latency + '0x01'+'0x00' + '1110'+'001x' + '000x'+'0001' + '0001'+'0000',
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'ca4': latency + '0110'+'0010' + '1010'+'000x' + '001x'+'0110' + '0000'+'0001',
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'ca5': latency + '0010'+'0100' + '1001'+'001x' + '000x'+'1101' + '0010'+'0010',
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}},
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)
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