Merge pull request #23 from JohnSully/outoforder

Out of Order Completion

litedram/common.py

@@ -64,6 +64,7 @@ def data_layout(dw):
     return [
         ("wdata",           dw, DIR_M_TO_S),
         ("wdata_we",     dw//8, DIR_M_TO_S),
+        ("wbank", bankbits_max, DIR_S_TO_M),
         ("rdata",           dw, DIR_S_TO_M),
         ("rbank", bankbits_max, DIR_S_TO_M)
     ]
@@ -86,11 +87,14 @@ def cmd_description(aw):
         ("adr", aw)
     ]
 
-def wdata_description(dw):
-    return [
+def wdata_description(dw, with_bank):
+    r = [
         ("data", dw),
         ("we",   dw//8)
     ]
+    if with_bank:
+        r += [("bank", bankbits_max)]
+    return r
 
 def rdata_description(dw, with_bank):
     r = [("data", dw)]
@@ -101,7 +105,7 @@ def rdata_description(dw, with_bank):
 
 class LiteDRAMPort:
     def __init__(self, mode, aw, dw, cd="sys", id=0,
-        with_rdata_bank=False):
+        reorder=False):
         self.mode = mode
         self.aw = aw
         self.dw = dw
@@ -110,10 +114,14 @@ class LiteDRAMPort:
 
         self.lock = Signal()
 
-        self.cmd = stream.Endpoint(cmd_description(aw))
-        self.wdata = stream.Endpoint(wdata_description(dw))
-        self.rdata = stream.Endpoint(rdata_description(dw, with_rdata_bank))
+        self.reorder = reorder
 
+        self.cmd = stream.Endpoint(cmd_description(aw))
+        self.wdata = stream.Endpoint(wdata_description(dw, reorder))
+        self.rdata = stream.Endpoint(rdata_description(dw, reorder))
+
+        if reorder:
+            print("WARNING: Reordering controller is experimental")
         self.flush = Signal()
 
 

litedram/frontend/crossbar.py

@@ -26,19 +26,19 @@ class LiteDRAMCrossbar(Module):
 
         self.masters = []
 
-    def get_port(self, mode="both", dw=None, cd="sys", reverse=False):
+    def get_port(self, mode="both", dw=None, cd="sys", reverse=False, reorder=False):
         if self.finalized:
             raise FinalizeError
         if dw is None:
             dw = self.dw
 
         # crossbar port
-        port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters))
+        port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters), reorder)
         self.masters.append(port)
 
         # clock domain crossing
         if cd != "sys":
-            new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id)
+            new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id, reorder)
             self.submodules += LiteDRAMPortCDC(new_port, port)
             port = new_port
 
@@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module):
                 adr_shift = -log2_int(dw//self.dw)
             else:
                 adr_shift = log2_int(self.dw//dw)
-            new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id)
+            new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id, reorder)
             self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse))
             port = new_port
 
@@ -70,6 +70,7 @@ class LiteDRAMCrossbar(Module):
         self.submodules += arbiters
 
         rbank = Signal(max=self.nbanks)
+        wbank = Signal(max=self.nbanks)
         for nb, arbiter in enumerate(arbiters):
             bank = getattr(controller, "bank"+str(nb))
 
@@ -77,6 +78,7 @@ class LiteDRAMCrossbar(Module):
             master_locked = []
             for nm, master in enumerate(self.masters):
                 locked = 0
+                if not master.reorder:
                     for other_nb, other_arbiter in enumerate(arbiters):
                         if other_nb != nb:
                             other_bank = getattr(controller, "bank"+str(other_nb))
@@ -94,6 +96,12 @@ class LiteDRAMCrossbar(Module):
             # Get rdata source bank
             self.sync += If((arbiter.grant == nm) & bank.rdata_valid, rbank.eq(nb))
 
+            # Get wdata source bank
+            self.sync += \
+                If((arbiter.grant == nm) & bank.wdata_ready,
+                    wbank.eq(nb)
+                )
+
             # route requests
             self.comb += [
                 bank.adr.eq(Array(m_rca)[arbiter.grant]),
@@ -126,6 +134,11 @@ class LiteDRAMCrossbar(Module):
             new_master_rbank = Signal(max=self.nbanks)
             self.sync += new_master_rbank.eq(rbank)
             rbank = new_master_rbank
+        # Delay wbank output to match wready
+        for i in range(self.write_latency-1):
+            new_master_wbank = Signal(max=self.nbanks)
+            self.sync += new_master_wbank.eq(wbank)
+            wbank = new_master_wbank
 
         for master, master_ready in zip(self.masters, master_readys):
             self.comb += master.cmd.ready.eq(master_ready)
@@ -152,6 +165,7 @@ class LiteDRAMCrossbar(Module):
             self.comb += master.rdata.data.eq(self.controller.rdata)
             if hasattr(master.rdata, "bank"):
                 self.comb += master.rdata.bank.eq(rbank)
+                self.comb += master.wdata.bank.eq(wbank)
 
     def split_master_addresses(self, bank_bits, rca_bits, cba_shift):
         m_ba = []    # bank address