Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/model: fix memory addressing issues in some configurations

This commit is contained in:
Piotr Binkowski 2020-02-17 12:21:31 +01:00
parent 9083822a74
commit ef0086e720
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litedram/phy/model.py
View File

@ -62,13 +62,13 @@ class BankModel(Module):
rdaddr = Signal(max=bank_mem_len)
self.comb += [
wraddr.eq(row*ncols | self.write_col),
rdaddr.eq(row*ncols | self.read_col),
wraddr.eq((row*ncols | self.write_col)[log2_int(burst_length*nphases):]),
rdaddr.eq((row*ncols | self.read_col)[log2_int(burst_length*nphases):]),
]
self.comb += [
If(active,
write_port.adr.eq(wraddr[log2_int(burst_length*nphases):]),
write_port.adr.eq(wraddr),
write_port.dat_w.eq(self.write_data),
If(we_granularity,
write_port.we.eq(Replicate(self.write, data_width//8) & ~self.write_mask),
@ -76,7 +76,7 @@ class BankModel(Module):
write_port.we.eq(self.write),
),
If(self.read,
read_port.adr.eq(rdaddr[log2_int(burst_length*nphases):]),
read_port.adr.eq(rdaddr),
self.read_data.eq(read_port.dat_r)
)
)