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bench/common: Cleanup, Increase sys_clk measure time to 5s.

This commit is contained in:
Florent Kermarrec 2021-03-12 14:29:43 +01:00
parent 3f9759b83b
commit f17037fdb2
1 changed files with 10 additions and 6 deletions
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16
bench/common.py
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@ -203,19 +203,21 @@ def s7_set_sys_clk(clk_freq, vco_freq):
# # #
# (Re)Configuring sys_clk.
print("Configuring sys_clk to {:3.3f}...".format(clk_freq/1e6))
print("Configuring sys_clk to {:3.3f}MHz...".format(clk_freq/1e6))
s7pll = S7PLL(bus)
clkout0_clkreg1 = ClkReg1(s7pll.read(0x8))
vco_div = int(vco_freq/clk_freq)
clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
clkout0_clkreg1.low_time = vco_div//2
s7pll.write(0x08, clkout0_clkreg1.pack())
# Measure/verify sys_clk
duration = 1
print("Measuring sys_clk...", end=" ");
duration = 5
start = bus.regs.crg_sys_clk_counter.read()
time.sleep(duration)
end = bus.regs.crg_sys_clk_counter.read()
print("Measured sys_clk: {:3.2f}MHz.".format((end-start)/(1e6*duration)))
print(": {:3.2f}MHz.".format((end-start)/(1e6*duration)))
# # #
@ -298,19 +300,21 @@ def us_set_sys_clk(clk_freq, vco_freq):
# # #
# (Re)Configuring sys_clk.
print("Configuring sys_clk to {:3.3f}...".format(clk_freq/1e6))
print("Configuring sys_clk to {:3.3f}MHz...".format(clk_freq/1e6))
uspll = USPLL(bus)
clkout0_clkreg1 = ClkReg1(uspll.read(0x8))
vco_div = int(vco_freq/clk_freq)
clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
clkout0_clkreg1.low_time = vco_div//2
uspll.write(0x08, clkout0_clkreg1.pack())
# Measure/verify sys_clk
duration = 1
print("Measuring sys_clk...", end=" ");
duration = 5
start = bus.regs.crg_sys_clk_counter.read()
time.sleep(duration)
end = bus.regs.crg_sys_clk_counter.read()
print("Measured sys_clk: {:3.2f}MHz.".format((end-start)/(1e6*duration)))
print(": {:3.2f}MHz.".format((end-start)/(1e6*duration)))
# # #