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frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid

This commit is contained in:
Florent Kermarrec 2020-02-19 18:34:55 +01:00
parent ebaf612089
commit f1dba787f6
1 changed files with 1 additions and 1 deletions
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litedram/frontend/dma.py
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@ -240,7 +240,7 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
self._sink.data.eq(self.sink.data), self._sink.data.eq(self.sink.data),
self._sink.address.eq(base + offset), self._sink.address.eq(base + offset),
self.sink.ready.eq(self._sink.ready), self.sink.ready.eq(self._sink.ready),
If(self.sink.ready, If(self.sink.valid & self.sink.ready,
NextValue(offset, offset + 1), NextValue(offset, offset + 1),
If(offset == (length - 1), If(offset == (length - 1),
If(self._loop.storage, If(self._loop.storage,