frontend/avalon: Improve decoupling in START state.
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@ -46,12 +46,11 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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# Internal Signals.
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burst_count = Signal(9)
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burst_start = Signal()
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address = Signal(port.address_width)
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address_offset = Signal(port.address_width)
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byteenable = Signal(avalon_data_width//8)
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writedata = Signal(avalon_data_width)
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start = Signal()
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latch = Signal()
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cmd_ready_seen = Signal()
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cmd_ready_count = Signal(9)
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@ -65,7 +64,7 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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]
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self.sync += [
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If(start,
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If(latch,
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byteenable.eq(avalon.byteenable),
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writedata.eq(avalon.writedata),
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burst_count.eq(avalon.burstcount),
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@ -77,31 +76,30 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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self.fsm = fsm = FSM(reset_state="START")
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fsm.act("START",
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avalon.waitrequest.eq(1),
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If(avalon.burstcount <= 1,
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port.cmd.addr.eq(avalon.address - address_offset),
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port.cmd.we.eq(avalon.write),
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port.cmd.valid.eq(avalon.read | avalon.write)
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),
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# Start of Access.
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If(avalon.read | avalon.write,
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If((avalon.burstcount > 1) | (downconvert == True) | port.cmd.ready,
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start.eq(1),
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If((downconvert == False) & (avalon.burstcount <= 1),
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avalon.waitrequest.eq(0)
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),
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latch.eq(1),
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# Burst Access.
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If(avalon.burstcount > 1,
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If(avalon.write,
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If(avalon.burstcount > 1,
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NextState("BURST_WRITE")
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).Else(
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port.cmd.last.eq(1),
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NextState("BURST_WRITE")
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),
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If(avalon.read,
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avalon.waitrequest.eq(0),
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NextValue(cmd_ready_count, avalon.burstcount),
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NextState("BURST_READ")
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)
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# Single Access.
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).Else(
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port.cmd.addr.eq(avalon.address - address_offset),
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port.cmd.we.eq(avalon.write),
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port.cmd.valid.eq(1),
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port.cmd.last.eq(1),
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If((downconvert == True) | port.cmd.ready,
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avalon.waitrequest.eq(downconvert == True),
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If(port.cmd.we,
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NextState("SINGLE_WRITE")
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)
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).Elif(avalon.read,
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If(avalon.burstcount > 1,
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avalon.waitrequest.eq(0),
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NextValue(cmd_ready_count, avalon.burstcount),
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NextState("BURST_READ")
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).Else(
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port.cmd.last.eq(1),
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NextState("SINGLE_READ")
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)
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)
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