sdram_init/ddr4: set data mask enable bit

2019-02-02 23:14:30 +01:00 · 2019-02-02 23:14:30 +01:00 · f2074542a1
parent 6d09a47103
commit f2074542a1
1 changed files with 1 additions and 1 deletions
--- a/litedram/sdram_init.py
+++ b/litedram/sdram_init.py
@ -320,7 +320,7 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
        mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
        mr3 = 0
        mr4 = 0
-        mr5 = 0
+        mr5 = 1 << 10 # data mask enable
        mr6 = format_mr6(4) # FIXME: tCCD

        init_sequence = [