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Default to HW control for sim 

(needs corresponding sdram.c fix in litex)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-06-01 20:13:59 +10:00
parent f23cb8056d
commit f3f89ed8d1
1 changed files with 5 additions and 1 deletions
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6
litedram/dfii.py
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@ -49,7 +49,11 @@ class DFIInjector(Module, AutoCSR):
self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
self._control = CSRStorage(4) # sel, cke, odt, reset_n # sel, cke, odt, reset_n
#
# sel defaults 1 (HW control) so sim models don't need to perform
# the initialization sequence
self._control = CSRStorage(4, reset=0x01)
for n, phase in enumerate(inti.phases): for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase)) setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))