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core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)

This commit is contained in:
Florent Kermarrec 2018-07-16 18:39:59 +02:00
parent eee89d4035
commit f4ad65e3c4
1 changed files with 8 additions and 5 deletions
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13
litedram/core/controller.py
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@ -26,11 +26,14 @@ class LiteDRAMController(Module):
self.settings.geom = geom_settings
self.settings.timing = timing_settings
if settings.phy.memtype in ["SDR"]:
burst_length = phy_settings.nphases*1 # command multiplication*SDR
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)
burst_lengths = {
"SDR": 1,
"DDR": 4,
"LPDDR": 4,
"DDR2": 4,
"DDR3": 8
}
address_align = log2_int(burst_lengths[phy_settings.memtype])
self.dfi = dfi.Interface(geom_settings.addressbits,
geom_settings.bankbits,