Merge pull request #360 from Dolu1990/master
litedram/address_mapping Add bank_byte_alignment
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f5e80bb010
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@ -40,7 +40,13 @@ class ControllerSettings(Settings):
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with_auto_precharge = True,
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# Address mapping
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address_mapping = "ROW_BANK_COL"):
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address_mapping = "ROW_BANK_COL",
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# bank_byte_alignment specify how many bytes should be in between each bank change (minimum).
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# This is usefull when you want to match a L2 cache sets size.
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# For instance you have a L2 cache of 256KB with 4 ways => Sets size of 256KB/4=64KB
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# => Ideal bank_byte_alignment = 0x10000
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bank_byte_alignment = 0):
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self.set_attributes(locals())
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# Controller ---------------------------------------------------------------------------------------
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@ -127,7 +127,7 @@ class LiteDRAMCrossbar(Module):
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nmasters = len(self.masters)
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# Address mapping --------------------------------------------------------------------------
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cba_shifts = {"ROW_BANK_COL": controller.settings.geom.colbits - controller.address_align}
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cba_shifts = {"ROW_BANK_COL": max(controller.settings.geom.colbits - controller.address_align, log2_int(controller.settings.bank_byte_alignment //(controller.data_width // 8))) }
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cba_shift = cba_shifts[controller.settings.address_mapping]
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m_ba = [m.get_bank_address(self.bank_bits, cba_shift)for m in self.masters]
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m_rca = [m.get_row_column_address(self.bank_bits, self.rca_bits, cba_shift) for m in self.masters]
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