Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litedram_gen: fix LiteDRAMECP5DDRPHYCRG clkin freq (input_clk_freq and not sys_clk_freq).

This commit is contained in:
Florent Kermarrec 2020-03-26 18:10:26 +01:00
parent 7fab898afc
commit f6babda683
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
litedram/gen.py
View File

@ -238,16 +238,16 @@ class LiteDRAMECP5DDRPHYCRG(Module):
# power on reset # power on reset
por_count = Signal(16, reset=2**16-1) por_count = Signal(16, reset=2**16-1)
por_done = Signal() por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal()) self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0) self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll # pll
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk, core_config['sys_clk_freq']) pll.register_clkin(clk, core_config["input_clk_freq"])
pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"]) pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"])
pll.create_clkout(self.cd_init, core_config['init_clk_freq']) pll.create_clkout(self.cd_init, core_config["init_clk_freq"])
self.specials += [ self.specials += [
Instance("ECLKSYNCB", Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk, i_ECLKI = self.cd_sys2x_i.clk,
@ -260,7 +260,7 @@ class LiteDRAMECP5DDRPHYCRG(Module):
i_RST = self.cd_sys2x.rst, i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk), o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst) AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst),
] ]
class LiteDRAMS7DDRPHYCRG(Module): class LiteDRAMS7DDRPHYCRG(Module):
@ -350,7 +350,7 @@ class LiteDRAMCore(SoCSDRAM):
pads = platform.request("ddram"), pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop) self.comb += crg.stop.eq(self.ddrphy.init.stop)
self.add_constant("ECP5DDRPHY", None) self.add_constant("ECP5DDRPHY")
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2") sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
# S7DDRPHY # S7DDRPHY
if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
@ -575,7 +575,7 @@ def main():
builder_arguments = builder_argdict(args) builder_arguments = builder_argdict(args)
builder_arguments["compile_gateware"] = False builder_arguments["compile_gateware"] = False
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, integrated_sram_size=0x1000) soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
builder = Builder(soc, **builder_arguments) builder = Builder(soc, **builder_arguments)
vns = builder.build(build_name="litedram_core", regular_comb=False) vns = builder.build(build_name="litedram_core", regular_comb=False)