core: make rdata_bank optional (break cdc when enabled), fix some usecases

litedram/common.py

@@ -92,12 +92,16 @@ def wdata_description(dw):
         ("we",   dw//8)
     ]
 
-def rdata_description(dw):
-    return [("data", dw), ("bank", bankbits_max)]
+def rdata_description(dw, with_bank):
+    r = [("data", dw)]
+    if with_bank:
+        r += [("bank", bankbits_max)]
+    return r
 
 
 class LiteDRAMPort:
-    def __init__(self, mode, aw, dw, cd="sys", id=0):
+    def __init__(self, mode, aw, dw, cd="sys", id=0,
+        with_rdata_bank=False):
         self.mode = mode
         self.aw = aw
         self.dw = dw
@@ -108,7 +112,7 @@ class LiteDRAMPort:
 
         self.cmd = stream.Endpoint(cmd_description(aw))
         self.wdata = stream.Endpoint(wdata_description(dw))
-        self.rdata = stream.Endpoint(rdata_description(dw))
+        self.rdata = stream.Endpoint(rdata_description(dw, with_rdata_bank))
 
         self.flush = Signal()
 

litedram/core/multiplexer.py

@@ -122,7 +122,7 @@ class Multiplexer(Module, AutoCSR):
         if settings.phy.nphases == 1:
             self.comb += [
                 choose_cmd.want_cmds.eq(1),
-                choose_cmd.want_activates(activate_allowed),
+                choose_cmd.want_activates.eq(activate_allowed),
                 choose_req.want_cmds.eq(1)
             ]
 
@@ -138,10 +138,10 @@ class Multiplexer(Module, AutoCSR):
         # tRRD Command Timing
         trrd = settings.timing.tRRD
         trrd_allowed = Signal(reset=1)
+        is_act_cmd = Signal()
+        self.comb += is_act_cmd.eq(choose_cmd.cmd.ras & ~choose_cmd.cmd.cas & ~choose_cmd.cmd.we)
         if trrd is not None:
             trrd_count = Signal(max=trrd+1)
-            is_act_cmd = Signal()
-            self.comb += is_act_cmd.eq(choose_cmd.cmd.ras & ~choose_cmd.cmd.cas & ~choose_cmd.cmd.we)
             self.sync += \
                 If(choose_cmd.cmd.ready & choose_cmd.cmd.valid & is_act_cmd,
                     trrd_count.eq(trrd-1)
@@ -181,17 +181,20 @@ class Multiplexer(Module, AutoCSR):
             self.comb += cas_allowed.eq(cas_count == 0)
         self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
 
-        # tWTR timing
-        tWTR = settings.timing.tWTR + settings.timing.tCCD # tWTR begins after the transfer is complete, tccd accounts for this
+        # Write to Read
         wtr_allowed = Signal(reset=1)
-        wtr_count = Signal(max=tWTR)
+        twtr = settings.timing.tWTR
+        if tccd is not None:
+            twtr += settings.timing.tCCD # tWTR begins after the transfer is complete, tCCD accounts for this
+        wtr_count = Signal(max=twtr+1)
         self.sync += [
             If(choose_req.cmd.ready & choose_req.cmd.valid & choose_req.cmd.is_write,
-                wtr_count.eq(tWTR-1)
+                wtr_count.eq(twtr-1)
             ).Elif(wtr_count != 0,
                 wtr_count.eq(wtr_count-1)
             )
         ]
+        self.comb += wtr_allowed.eq(wtr_count == 0)
 
         # Read/write turnaround
         read_available = Signal()
@@ -300,7 +303,7 @@ class Multiplexer(Module, AutoCSR):
             )
         )
         fsm.act("WTR",
-            If(wtr_count == 0,
+            If(wtr_allowed,
                 NextState("READ")
             )
         )

litedram/frontend/crossbar.py

@@ -150,7 +150,8 @@ class LiteDRAMCrossbar(Module):
         # route data reads
         for master in self.masters:
             self.comb += master.rdata.data.eq(self.controller.rdata)
-            self.comb += master.rdata.bank.eq(rbank)
+            if hasattr(master.rdata, "bank"):
+                self.comb += master.rdata.bank.eq(rbank)
 
     def split_master_addresses(self, bank_bits, rca_bits, cba_shift):
         m_ba = []    # bank address