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phy/kusddrphy: verify latencies with simulation

This commit is contained in:
Florent Kermarrec 2017-07-06 19:21:38 +02:00
parent abf028e0be
commit fa3535f7c0
1 changed files with 5 additions and 3 deletions
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8
litedram/phy/kusddrphy.py
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@ -10,7 +10,6 @@ from litedram.common import PhySettings
from litedram.phy.dfi import * from litedram.phy.dfi import *
# TODO: # TODO:
# - verify read_latency in simulation (OSERDESE3/ISERDESE3)
# - verify initial p_DELAY_VALUE on ODELAYE3/IDELAYE3 # - verify initial p_DELAY_VALUE on ODELAYE3/IDELAYE3
# - simulate with Micron's model # - simulate with Micron's model
# - test on board # - test on board
@ -24,10 +23,13 @@ class KUSDDRPHY(Module, AutoCSR):
self._wlevel_en = CSRStorage() self._wlevel_en = CSRStorage()
self._wlevel_strobe = CSR() self._wlevel_strobe = CSR()
self._dly_sel = CSRStorage(databits//8) self._dly_sel = CSRStorage(databits//8)
self._rdly_dq_rst = CSR() self._rdly_dq_rst = CSR()
self._rdly_dq_inc = CSR() self._rdly_dq_inc = CSR()
self._rdly_dq_bitslip = CSRStorage(3) self._rdly_dq_bitslip = CSRStorage(3)
self._wdly_dq_rst = CSR() self._wdly_dq_rst = CSR()
self._wdly_dq_inc = CSR() self._wdly_dq_inc = CSR()
self._wdly_dqs_rst = CSR() self._wdly_dqs_rst = CSR()
@ -273,9 +275,9 @@ class KUSDDRPHY(Module, AutoCSR):
# Flow control # Flow control
# #
# total read latency = 8: # total read latency = 8:
# 2 cycles through OSERDESE3 TODO: verify latency # 2 cycles through OSERDESE3
# 2 cycles CAS # 2 cycles CAS
# 2 cycles through ISERDESE3 TODO: verify latency # 2 cycles through ISERDESE3
# 2 cycles through BitSlip # 2 cycles through BitSlip
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
for i in range(8-1): for i in range(8-1):