Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/gensdrphy: make CAS latency configurable

This commit is contained in:
Florent Kermarrec 2019-01-07 23:01:46 +01:00
parent b4ee95c3e3
commit fc3a192a87
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
litedram/phy/gensdrphy.py
View File

@ -10,8 +10,6 @@
# Assert dfi_rddata_en in the same cycle as the read command. The data will come # Assert dfi_rddata_en in the same cycle as the read command. The data will come
# back on dfi_rddata 4 cycles later, along with the assertion of dfi_rddata_valid. # back on dfi_rddata 4 cycles later, along with the assertion of dfi_rddata_valid.
# #
# This SDR PHY only supports CAS Latency 2.
#
from migen import * from migen import *
from migen.genlib.record import * from migen.genlib.record import *
@ -22,7 +20,7 @@ from litedram.phy.dfi import *
class GENSDRPHY(Module): class GENSDRPHY(Module):
def __init__(self, pads): def __init__(self, pads, cl=2):
addressbits = len(pads.a) addressbits = len(pads.a)
bankbits = len(pads.ba) bankbits = len(pads.ba)
nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n) nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
@ -37,8 +35,8 @@ class GENSDRPHY(Module):
wrphase=0, wrphase=0,
rdcmdphase=0, rdcmdphase=0,
wrcmdphase=0, wrcmdphase=0,
cl=2, cl=cl,
read_latency=4, read_latency=cl + 2,
write_latency=0 write_latency=0
) )
@ -81,6 +79,6 @@ class GENSDRPHY(Module):
self.sync += wrdata_en.eq(dfi.p0.wrdata_en) self.sync += wrdata_en.eq(dfi.p0.wrdata_en)
self.comb += dq_oe.eq(wrdata_en) self.comb += dq_oe.eq(wrdata_en)
rddata_en = Signal(4) rddata_en = Signal(cl + 2)
self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en[:3])) self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en[:cl + 1]))
self.comb += dfi.p0.rddata_valid.eq(rddata_en[3]) self.comb += dfi.p0.rddata_valid.eq(rddata_en[cl + 1])