test: add option to benchmark predefined access patterns
This commit is contained in:
Jędrzej Boczar
parent
4a3ad56146
commit
fcbcd4d3fe
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@ -185,6 +185,60 @@ class _LiteDRAMBISTGenerator(Module):
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raise NotImplementedError
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self.comb += dma.sink.data.eq(data_gen.o)
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@ResetInserter()
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class _LiteDRAMPatternGenerator(Module):
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def __init__(self, dram_port, init=[]):
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ashift, awidth = get_ashift_awidth(dram_port)
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self.start = Signal()
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self.done = Signal()
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self.ticks = Signal(32)
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# # #
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# DMA --------------------------------------------------------------------------------------
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dma = LiteDRAMDMAWriter(dram_port)
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self.submodules += dma
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cmd_counter = Signal(dram_port.address_width, reset_less=True)
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# Data / Address FSM -----------------------------------------------------------------------
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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NextValue(cmd_counter, 0),
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NextState("RUN")
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),
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NextValue(self.ticks, 0)
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)
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fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (len(init) - 1),
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NextState("DONE")
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)
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),
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NextValue(self.ticks, self.ticks + 1)
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)
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fsm.act("DONE",
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self.done.eq(1)
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)
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if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
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dma_sink_addr = dma.sink.address
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elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
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dma_sink_addr = dma.sink.address[ashift:]
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else:
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raise NotImplementedError
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addr_cases = {i: dma_sink_addr.eq(addr) for i, (addr, data) in enumerate(init)}
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data_cases = {i: dma.sink.data.eq(data) for i, (addr, data) in enumerate(init)}
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self.comb += [
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Case(cmd_counter, addr_cases),
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Case(cmd_counter, data_cases),
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]
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# LiteDRAMBISTGenerator ----------------------------------------------------------------------------
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class LiteDRAMBISTGenerator(Module, AutoCSR):
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@ -367,6 +421,88 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
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self.done.eq(1)
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)
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@ResetInserter()
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class _LiteDRAMPatternChecker(Module, AutoCSR):
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def __init__(self, dram_port, init=[]):
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ashift, awidth = get_ashift_awidth(dram_port)
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self.start = Signal()
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self.done = Signal()
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self.ticks = Signal(32)
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self.errors = Signal(32)
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# # #
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# DMA --------------------------------------------------------------------------------------
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dma = LiteDRAMDMAReader(dram_port)
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self.submodules += dma
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# Address FSM ------------------------------------------------------------------------------
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cmd_counter = Signal(dram_port.address_width, reset_less=True)
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cmd_fsm = FSM(reset_state="IDLE")
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self.submodules += cmd_fsm
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cmd_fsm.act("IDLE",
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If(self.start,
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NextValue(cmd_counter, 0),
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NextState("RUN")
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)
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)
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cmd_fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (len(init) - 1),
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NextState("DONE")
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)
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)
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)
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cmd_fsm.act("DONE")
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if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
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dma_addr_sink = dma.sink.address
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elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
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dma_addr_sink = dma.sink.address[ashift:]
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else:
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raise NotImplementedError
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addr_cases = {i: dma_addr_sink.eq(addr) for i, (addr, data) in enumerate(init)}
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self.comb += Case(cmd_counter, addr_cases)
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# Data FSM ---------------------------------------------------------------------------------
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data_counter = Signal(dram_port.address_width, reset_less=True)
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expected_data = Signal.like(dma.source.data)
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data_cases = {i: expected_data.eq(data) for i, (addr, data) in enumerate(init)}
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self.comb += Case(data_counter, data_cases)
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data_fsm = FSM(reset_state="IDLE")
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self.submodules += data_fsm
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data_fsm.act("IDLE",
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If(self.start,
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NextValue(data_counter, 0),
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NextValue(self.errors, 0),
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NextState("RUN")
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),
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NextValue(self.ticks, 0)
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)
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data_fsm.act("RUN",
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dma.source.ready.eq(1),
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If(dma.source.valid,
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NextValue(data_counter, data_counter + 1),
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If(dma.source.data != expected_data,
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NextValue(self.errors, self.errors + 1)
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),
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If(data_counter == (len(init) - 1),
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NextState("DONE")
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)
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),
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NextValue(self.ticks, self.ticks + 1)
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)
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data_fsm.act("DONE",
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self.done.eq(1)
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)
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# LiteDRAMBISTChecker ------------------------------------------------------------------------------
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class LiteDRAMBISTChecker(Module, AutoCSR):
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@ -3,6 +3,7 @@
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import csv
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import argparse
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from migen import *
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@ -16,9 +17,8 @@ from litex.soc.integration.builder import *
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from litex.tools.litex_sim import SimSoC
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker, \
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_LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
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# LiteDRAM Benchmark SoC ---------------------------------------------------------------------------
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@ -29,6 +29,7 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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bist_base = 0x00000000,
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bist_length = 1024,
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bist_random = False,
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pattern_init = None,
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**kwargs):
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# SimSoC -----------------------------------------------------------------------------------
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@ -42,12 +43,34 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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# make sure that we perform at least one access
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bist_length = max(bist_length, self.sdram.controller.interface.data_width // 8)
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# BIST Generator ---------------------------------------------------------------------------
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bist_generator = _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
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self.submodules.bist_generator = bist_generator
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# BIST Generator / Checker -----------------------------------------------------------------
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if pattern_init is None:
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bist_generator = _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
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bist_checker = _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
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# BIST Checker -----------------------------------------------------------------------------
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bist_checker = _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
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generator_config = [
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bist_generator.base.eq(bist_base),
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bist_generator.length.eq(bist_length),
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bist_generator.random.eq(bist_random),
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]
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checker_config = [
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bist_checker.base.eq(bist_base),
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bist_checker.length.eq(bist_length),
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bist_checker.random.eq(bist_random),
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]
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else:
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# TODO: run checker in parallel to avoid overwriting previously written data
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address_set = set()
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for addr, _ in pattern_init:
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assert addr not in address_set, \
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'Duplicate address 0x%08x in pattern_init, write will overwrite previous value!' % addr
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address_set.add(addr)
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bist_generator = _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=pattern_init)
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bist_checker = _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=pattern_init)
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generator_config = checker_config = []
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self.submodules.bist_generator = bist_generator
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self.submodules.bist_checker = bist_checker
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# Sequencer --------------------------------------------------------------------------------
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@ -68,18 +91,14 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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)
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fsm.act("BIST-GENERATOR",
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bist_generator.start.eq(1),
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bist_generator.base.eq(bist_base),
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bist_generator.length.eq(bist_length),
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bist_generator.random.eq(bist_random),
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*generator_config,
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If(bist_generator.done,
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NextState("BIST-CHECKER")
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)
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)
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fsm.act("BIST-CHECKER",
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bist_checker.start.eq(1),
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bist_checker.base.eq(bist_base),
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bist_checker.length.eq(bist_length),
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bist_checker.random.eq(bist_random),
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*checker_config,
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If(bist_checker.done,
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NextState("DISPLAY")
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)
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@ -113,16 +132,17 @@ def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Benchmark SoC Simulation")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
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parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
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parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
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parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
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parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
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parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
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parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
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parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
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parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
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parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
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args = parser.parse_args()
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soc_kwargs = soc_sdram_argdict(args)
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@ -138,6 +158,12 @@ def main():
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soc_kwargs["bist_length"] = int(args.bist_length, 0)
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soc_kwargs["bist_random"] = args.bist_random
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if args.access_pattern:
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with open(args.access_pattern, newline='') as f:
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reader = csv.reader(f)
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pattern_init = [(int(addr, 0), int(data, 0)) for addr, data in reader]
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soc_kwargs["pattern_init"] = pattern_init
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# SoC ------------------------------------------------------------------------------------------
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soc = LiteDRAMBenchmarkSoC(**soc_kwargs)
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