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phy/control: cleanup/simplify (no functional changes).

This commit is contained in:
Florent Kermarrec 2020-04-15 11:15:00 +02:00
parent a7676189b5
commit fdf7c7613c
3 changed files with 26 additions and 25 deletions
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31
litedram/phy/ecp5ddrphy.py
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@ -426,29 +426,30 @@ class ECP5DDRPHY(Module, AutoCSR):
# Read Control Path ------------------------------------------------------------------------
# Read latency = ODDRX2DQA latency + cl_sys_latency + IDDRX2DQA latency + Bitslip latency.
rddata_en = dfi.phases[self.settings.rdphase].rddata_en
rddata_ens = Array([Signal() for i in range(self.settings.read_latency-1)])
for i in range(self.settings.read_latency-1):
for i in range(self.settings.read_latency - 1):
n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en)
self.comb += rddata_ens[i].eq(rddata_en)
if i in [cl_sys_latency + 1, cl_sys_latency + 2]:
self.comb += If(rddata_en, dqs_read.eq(1))
rddata_en = n_rddata_en
self.sync += [phase.rddata_valid.eq(rddata_en)
for phase in dfi.phases]
self.comb += dqs_read.eq(rddata_ens[cl_sys_latency+1] | rddata_ens[cl_sys_latency+2])
self.sync += [phase.rddata_valid.eq(rddata_en) for phase in dfi.phases]
# Write Control Path -----------------------------------------------------------------------
oe = Signal()
last_wrdata_en = Signal(cwl_sys_latency+3)
last_wrdata_en = Signal(cwl_sys_latency + 3)
wrphase = dfi.phases[self.settings.wrphase]
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en))
self.comb += oe.eq(
last_wrdata_en[cwl_sys_latency-1] |
last_wrdata_en[cwl_sys_latency] |
last_wrdata_en[cwl_sys_latency+1] |
last_wrdata_en[cwl_sys_latency+2])
self.sync += oe_dqs.eq(oe), oe_dq.eq(oe)
self.sync += bl8_sel.eq(last_wrdata_en[cwl_sys_latency-1])
last_wrdata_en[cwl_sys_latency + -1] |
last_wrdata_en[cwl_sys_latency + 0] |
last_wrdata_en[cwl_sys_latency + 1] |
last_wrdata_en[cwl_sys_latency + 2])
self.sync += [
oe_dqs.eq(oe),
oe_dq.eq(oe),
bl8_sel.eq(last_wrdata_en[cwl_sys_latency - 1])
]
# Write DQS Postamble/Preamble Control Path ------------------------------------------------
self.sync += dqs_preamble.eq(last_wrdata_en[cwl_sys_latency-2])
self.sync += dqs_preamble.eq(last_wrdata_en[cwl_sys_latency - 2])
self.sync += dqs_postamble.eq(oe_dqs)

14
litedram/phy/s7ddrphy.py
View File

@ -569,7 +569,7 @@ class S7DDRPHY(Module, AutoCSR):
# Read Control Path ------------------------------------------------------------------------
# Read latency = OSERDESE2 latency + cl_sys_latency + ISERDESE2 latency + Bitslip latency.
rddata_en = dfi.phases[self.settings.rdphase].rddata_en
for i in range(self.settings.read_latency-1):
for i in range(self.settings.read_latency - 1):
n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en
@ -582,9 +582,9 @@ class S7DDRPHY(Module, AutoCSR):
# Write Control Path -----------------------------------------------------------------------
oe = Signal()
last_wrdata_en = Signal(cwl_sys_latency+2)
last_wrdata_en = Signal(cwl_sys_latency + 2)
wrphase = dfi.phases[self.settings.wrphase]
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en))
self.comb += oe.eq(
last_wrdata_en[cwl_sys_latency + -1] |
last_wrdata_en[cwl_sys_latency + 0] |
@ -605,12 +605,12 @@ class S7DDRPHY(Module, AutoCSR):
# Write DQS Postamble/Preamble Control Path ------------------------------------------------
if memtype == "DDR2":
dqs_sys_latency = cwl_sys_latency-1
dqs_sys_latency = cwl_sys_latency - 1
elif memtype == "DDR3":
dqs_sys_latency = cwl_sys_latency-1 if with_odelay else cwl_sys_latency
dqs_sys_latency = cwl_sys_latency - 1 if with_odelay else cwl_sys_latency
self.comb += [
dqs_preamble.eq(last_wrdata_en[dqs_sys_latency-1] & ~last_wrdata_en[dqs_sys_latency]),
dqs_postamble.eq(last_wrdata_en[dqs_sys_latency+1] & ~last_wrdata_en[dqs_sys_latency]),
dqs_preamble.eq(last_wrdata_en[dqs_sys_latency - 1] & ~last_wrdata_en[dqs_sys_latency]),
dqs_postamble.eq(last_wrdata_en[dqs_sys_latency + 1] & ~last_wrdata_en[dqs_sys_latency]),
]
# Xilinx Virtex7 (S7DDRPHY with odelay) ------------------------------------------------------------

6
litedram/phy/usddrphy.py
View File

@ -495,7 +495,7 @@ class USDDRPHY(Module, AutoCSR):
# Read Control Path ------------------------------------------------------------------------
# Read latency = OSERDESE3 latency + cl_sys_latency + ISERDESE3 latency + Bitslip latency.
rddata_en = dfi.phases[self.settings.rdphase].rddata_en
for i in range(self.settings.read_latency-1):
for i in range(self.settings.read_latency - 1):
n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en
@ -506,9 +506,9 @@ class USDDRPHY(Module, AutoCSR):
# Write Control Path -----------------------------------------------------------------------
oe = Signal()
last_wrdata_en = Signal(cwl_sys_latency+2)
last_wrdata_en = Signal(cwl_sys_latency + 2)
wrphase = dfi.phases[self.settings.wrphase]
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en))
self.comb += oe.eq(
last_wrdata_en[cwl_sys_latency + -1] |
last_wrdata_en[cwl_sys_latency + 0] |