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test: add option to run benchmarks with alternating write/read
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6093f2012e
commit
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1 changed files with 40 additions and 18 deletions
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@ -29,6 +29,7 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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bist_base = 0x00000000,
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bist_base = 0x00000000,
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bist_length = 1024,
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bist_length = 1024,
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bist_random = False,
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bist_random = False,
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bist_alternating = False,
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pattern_init = None,
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pattern_init = None,
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**kwargs):
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**kwargs):
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@ -58,13 +59,16 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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bist_checker.length.eq(bist_length),
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bist_checker.length.eq(bist_length),
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bist_checker.random.eq(bist_random),
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bist_checker.random.eq(bist_random),
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]
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]
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assert not (bist_random and not bist_alternating), \
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'Write to random address may overwrite previously written data before reading!'
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else:
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else:
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# TODO: run checker in parallel to avoid overwriting previously written data
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if not bist_alternating:
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address_set = set()
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address_set = set()
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for addr, _ in pattern_init:
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for addr, _ in pattern_init:
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assert addr not in address_set, \
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assert addr not in address_set, \
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'Duplicate address 0x%08x in pattern_init, write will overwrite previous value!' % addr
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'Duplicate address 0x%08x in pattern_init, write will overwrite previous value!' % addr
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address_set.add(addr)
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address_set.add(addr)
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bist_generator = _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=pattern_init)
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bist_generator = _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=pattern_init)
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bist_checker = _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=pattern_init)
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bist_checker = _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=pattern_init)
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@ -89,20 +93,36 @@ class LiteDRAMBenchmarkSoC(SimSoC):
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NextState("BIST-GENERATOR")
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NextState("BIST-GENERATOR")
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)
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)
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)
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)
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fsm.act("BIST-GENERATOR",
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if bist_alternating:
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bist_generator.start.eq(1),
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fsm.act("BIST-GENERATOR",
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*generator_config,
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bist_generator.start.eq(1),
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If(bist_generator.done,
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bist_checker.start.eq(1),
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NextState("BIST-CHECKER")
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# force generator to wait for checker and vice versa
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bist_generator.run.eq(bist_checker.ready),
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bist_checker.run.eq(bist_generator.ready),
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*generator_config,
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*checker_config,
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If(bist_checker.done,
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NextState("DISPLAY")
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)
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)
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)
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)
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else:
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fsm.act("BIST-CHECKER",
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fsm.act("BIST-GENERATOR",
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bist_checker.start.eq(1),
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bist_generator.start.eq(1),
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*checker_config,
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bist_generator.run.eq(1),
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If(bist_checker.done,
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*generator_config,
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NextState("DISPLAY")
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If(bist_generator.done,
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NextState("BIST-CHECKER")
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)
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)
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fsm.act("BIST-CHECKER",
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bist_checker.start.eq(1),
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bist_checker.run.eq(1),
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*checker_config,
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If(bist_checker.done,
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NextState("DISPLAY")
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)
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)
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)
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)
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fsm.act("DISPLAY",
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fsm.act("DISPLAY",
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display.eq(1),
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display.eq(1),
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NextState("FINISH")
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NextState("FINISH")
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@ -149,6 +169,7 @@ def main():
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
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parser.add_argument("--bist-alternating", action="store_true", help="Perform alternating writes/reads (WRWRWR... instead of WWW...RRR...)")
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parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
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parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -164,6 +185,7 @@ def main():
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soc_kwargs["bist_base"] = int(args.bist_base, 0)
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soc_kwargs["bist_base"] = int(args.bist_base, 0)
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soc_kwargs["bist_length"] = int(args.bist_length, 0)
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soc_kwargs["bist_length"] = int(args.bist_length, 0)
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soc_kwargs["bist_random"] = args.bist_random
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soc_kwargs["bist_random"] = args.bist_random
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soc_kwargs["bist_alternating"] = args.bist_alternating
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if args.access_pattern:
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if args.access_pattern:
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soc_kwargs["pattern_init"] = load_access_pattern(args.access_pattern)
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soc_kwargs["pattern_init"] = load_access_pattern(args.access_pattern)
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