10 Commits

Author	SHA1	Message	Date
Florent Kermarrec	248c5de517	bench: switch to UARTBone to simplify (and to allow testing boards without ethernet capability) and improve test.	2020-08-28 03:47:49 +02:00
Florent Kermarrec	6f2462b731	bench: add kc705.	2020-08-27 19:05:17 +02:00
Florent Kermarrec	d3502e6a9b	bench: add common.py with common bench test code.	2020-08-27 19:05:05 +02:00
Florent Kermarrec	2e3e19e9d4	bench: simplify/improve, working on arty/genesys2.	2020-08-27 18:41:54 +02:00
Florent Kermarrec	5c69da5d6d	bench: add initial kcu105 bench target.	2020-08-24 21:56:11 +02:00
Florent Kermarrec	9995c0fefb	bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. ... This simplifies software development.	2020-08-24 18:40:54 +02:00
Florent Kermarrec	ac825e5112	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
Florent Kermarrec	94241d0583	bench: use new platform.request_all on LedChaser.	2020-08-06 20:03:03 +02:00
Florent Kermarrec	74205979bd	bench: add genesys2 bench.	2020-08-06 19:19:45 +02:00
Florent Kermarrec	37fb44f33e	add bench directory with a first bench on arty board. ... The aim is to create an automated hardware bench, control is done over Etherbone (but could also be done over UARTBone, PCIe, USB, etc...) and various frequencies are tested and BIOS logged. It would also be useful to be able to recompile/reload BIOS in this bench to easily test software changes and verify it works with various frequencies. Can be tested with: ./arty.py --build --load lxserver --udp ./arty.py --test Dump Main PLL... ClkReg1: low_time: 8 high_time: 8 reserved: 1 phase_mux: 0 Reconfig Main PLL to 133.33333333333331MHz... Measuring sys_clk... sys_clk: 133.72MHz Reset SoC and get BIOS log... __ __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Aug 6 2020 18:49:15 BIOS CRC passed (44c8f057) Migen git sha1: 7bc4eb1 LiteX git sha1: 188e6f57 --=============== SoC ==================-- CPU: VexRiscv @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 32KiB SRAM: 8KiB L2: 8KiB MAIN-RAM: 262144KiB --========== Initialization ============-- Initializing DRAM @0x40000000... SDRAM now under software control SDRAM now under software control Read leveling: m0, b00: |00000000000000000000000000000000| delays: - m0, b01: |00000000000000000000000000000000| delays: - m0, b02: |00000000000000000000000000000000| delays: - m0, b03: |00000000000000000000000000000000| delays: - m0, b04: |00000000000000000000000000000000| delays: - m0, b05: |00000000000000000000000000000000| delays: - m0, b06: |00000000000000000000000000000000| delays: - m0, b07: |00000000000000000000000000000000| delays: - m0, b08: |00000000000000000000000000000000| delays: - m0, b09: |11111111111000000000000000000000| delays: 05+-05 m0, b10: |00000000000111111111110000000000| delays: 16+-05 m0, b11: |00000000000000000000000111111111| delays: 27+-04 m0, b12: |00000000000000000000000000000000| delays: - m0, b13: |00000000000000000000000000000000| delays: - m0, b14: |00000000000000000000000000000000| delays: - m0, b15: |00000000000000000000000000000000| delays: - best: m0, b09 delays: 05+-05 m1, b00: |00000000000000000000000000000000| delays: - m1, b01: |00000000000000000000000000000000| delays: - m1, b02: |00000000000000000000000000000000| delays: - m1, b03: |00000000000000000000000000000000| delays: - m1, b04: |00000000000000000000000000000000| delays: - m1, b05: |00000000000000000000000000000000| delays: - m1, b06: |00000000000000000000000000000000| delays: - m1, b07: |00000000000000000000000000000000| delays: - m1, b08: |00000000000000000000000000000000| delays: - m1, b09: |11111111111000000000000000000000| delays: 05+-05 m1, b10: |00000000000011111111111000000000| delays: 17+-05 m1, b11: |00000000000000000000000011111111| delays: 28+-04 m1, b12: |00000000000000000000000000000000| delays: - m1, b13: |00000000000000000000000000000000| delays: - m1, b14: |00000000000000000000000000000000| delays: - m1, b15: |00000000000000000000000000000000| delays: - best: m1, b09 delays: 05+-05 SDRAM now under hardware control Memtest at 0x40000000... [########################################] [########################################] Memtest OK Memspeed at 0x40000000... Writes: 212 Mbps Reads: 188 Mbps --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> Reconfig Main PLL to 114.28571428571428MHz...	2020-08-06 19:05:20 +02:00