3 Commits

Author	SHA1	Message	Date
Jędrzej Boczar	baf9c07858	phy/utils: improve ConstBitSlip: ... * optional register=False to decrease latency by 1 cycle * require explicit `cycles` as it influences latency (min_cycles still can be used) * add unit tests	2021-06-21 14:43:49 +02:00
Jędrzej Boczar	4a96be86c0	test/lpddr4: move run_simulation wrapper to phy_common.py	2021-06-21 14:43:49 +02:00
Jędrzej Boczar	8e563239f9	phy/lpddr4: extract common utilities	2021-06-21 13:22:15 +02:00