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0457910ec7

Merge pull request #50 from antmicro/mdudek/S7PHY_ddr5_support Tomasz Michalak 2022-10-27 17:12:11 +0200
28124e7ee1

Merge pull request #49 from antmicro/mdudek/better_tristate_support_ddr5 Tomasz Michalak 2022-10-26 15:17:24 +0200
7ec8a52200

Merge branch 'master' into tmr_bm Preston Brazzle 2022-10-25 11:30:34 -0400
8781d93508 Added with_tmr to settings pbrazzle 2022-10-25 11:27:25 -0400
5910b59e53 Improve timings in DDR5 PHY Maciej Dudek 2022-10-12 10:37:05 +0200
860e82e510 Fix DDR5 unit tests Maciej Dudek 2022-10-10 14:26:29 +0200
262a3ae860 Improve timings Maciej Dudek 2022-09-29 19:00:25 +0200
57c939fda0 Fix false paths Maciej Dudek 2022-09-29 17:09:09 +0200
425046185d Don't use cdc signals in basephy Rename wr taps, use correct names Maciej Dudek 2022-09-29 15:33:49 +0200
66a5f16a10 Rewrite DDR5 S7PHY There are still timing violations Maciej Dudek 2022-09-29 13:55:43 +0200
2bc1c0a826 Version 7.2.0 breaks pytest-parallel Maciej Dudek 2022-10-25 16:49:53 +0200
b66dff258a litedram_gen: increase integrated_rom_size to 0xC000 Maciej Dudek 2022-10-24 13:41:22 +0200
3c439827a9 Pindown Verilator version to last V4 release V5 version of verilator breaks on of LPDDR5 tests Maciej Dudek 2022-10-13 13:08:31 +0200
119cb500e7 Fix naming Maciej Dudek 2022-10-12 18:06:24 +0200
b676f3a6b7 Update LiteX branch Maciej Dudek 2022-09-27 13:45:52 +0200
c770dd62ed test/test_lpddr5: Add tINIT2 as allowed warning. Florent Kermarrec 2022-10-25 08:58:20 +0200
d1529d7508 ci: Bump to ubuntu 20.04. Florent Kermarrec 2022-10-14 18:17:02 +0200
2b6a7accc6 New Verilog pbrazzle 2022-10-14 10:40:05 -0400
107c574b7c Create Xilinx Oserdes model Update simulation to use Xilinx Oserdes model Maciej Dudek 2022-09-26 19:41:08 +0200
644b1fe802 Account for bitslip in ddr5 tests Maciej Dudek 2022-09-20 12:26:28 +0200
1111b39e1a Remove per dq bitslip adjustment as it would create to many oe signals. According to JEDEC, single DQS DQ group should be length match and only combinational delay should be used. Maciej Dudek 2022-09-09 15:09:06 +0200
e1903a779a Add tri state serialization to basephy and simphy Reintroduce BitSlips, they are required for running PHY on hardware Maciej Dudek 2022-09-08 17:28:41 +0200
77b9fec89b Fix oe signals for dq, dmi and dqs. Fix ddr5 tests Maciej Dudek 2022-09-07 19:23:26 +0200
917d90d904 Prepare for oe serialization with SERDES Maciej Dudek 2022-09-02 11:27:18 +0200
d2f3db8a9a New Verilog pbrazzle 2022-10-03 15:54:19 -0400
555c8b66b6 New Verilog pbrazzle 2022-10-03 15:24:56 -0400
27686fe981 New Verilog pbrazzle 2022-10-03 15:11:43 -0400
f43973a073 New Verilog pbrazzle 2022-10-03 14:54:44 -0400
fd7cd4809b New Verilog pbrazzle 2022-10-03 12:13:15 -0400
c1594cf1a7 New Verilog pbrazzle 2022-10-03 12:03:57 -0400
114fb4e5dc New Verilog pbrazzle 2022-10-03 11:44:33 -0400
60b3b7f85a New Verilog pbrazzle 2022-10-03 10:13:42 -0400
7603a755dd New Verilog pbrazzle 2022-10-03 09:47:25 -0400
dcb74af33c New Verilog pbrazzle 2022-10-03 09:23:22 -0400
922d7afc42 New Verilog pbrazzle 2022-10-03 08:54:09 -0400
a2f747da5e New Verilog pbrazzle 2022-10-02 15:06:27 -0400
29dbf205ac New Verilog pbrazzle 2022-10-02 15:01:43 -0400
3680b1e2a3 New Verilog pbrazzle 2022-10-02 14:34:58 -0400
8fc1c8c718 New Verilog pbrazzle 2022-10-02 13:18:57 -0400
f471c00946 New Verilog pbrazzle 2022-10-02 12:59:18 -0400
c310d4b0f2 New Verilog pbrazzle 2022-10-02 11:51:09 -0400
2a4caf53cd New Verilog pbrazzle 2022-09-30 11:50:06 -0400
6e17152139 New Verilog pbrazzle 2022-09-30 11:38:10 -0400
97924a6c80 New Verilog pbrazzle 2022-09-30 09:34:17 -0400
311e19f256 New Verilog pbrazzle 2022-09-30 08:43:28 -0400
28353b6071

Merge pull request #43 from antmicro/msieron/ddr5-s7phy Maciej Dudek 2022-09-29 16:56:58 +0200
045a528596 New Verilog pbrazzle 2022-09-28 13:17:49 -0400
07260d4eb1 New Verilog pbrazzle 2022-09-28 13:15:43 -0400
e51b8969ae New Verilog pbrazzle 2022-09-28 13:06:01 -0400
67d8bd9372 New Verilog pbrazzle 2022-09-28 12:55:47 -0400
c493d077fb New Verilog pbrazzle 2022-09-28 12:47:18 -0400
635ad7381c New Verilog pbrazzle 2022-09-28 12:34:49 -0400
4173462961 New Verilog pbrazzle 2022-09-28 12:25:49 -0400
f862773427 New Verilog pbrazzle 2022-09-28 12:15:48 -0400
b813c5c98f New Verilog pbrazzle 2022-09-28 12:14:32 -0400
536592a2ec New Verilog pbrazzle 2022-09-26 17:04:43 -0400
f4d2ef29a9 New Verilog pbrazzle 2022-09-26 16:54:36 -0400
f283921b07 New Verilog pbrazzle 2022-09-26 16:33:57 -0400
6ff0e08c52 New Verilog pbrazzle 2022-09-26 16:31:07 -0400
feb8bf7416 New Verilog pbrazzle 2022-09-26 16:29:01 -0400
7bc75e6dfd New Verilog pbrazzle 2022-09-26 16:26:34 -0400
ad9cd7c556 Adjust DDR5 S7PHY to work with sub channels Michal Sieron 2022-09-22 10:17:07 +0200
737d7a35f9 Fix things missed when adding sub channels Michal Sieron 2022-09-22 10:16:47 +0200
119a293dea Update S7PHY to work with reworked DFII PHY Michal Sieron 2022-08-31 11:55:31 +0200
6e9573d3ea New Verilog pbrazzle 2022-09-21 17:36:04 -0400
eea5546721 New Verilog pbrazzle 2022-09-21 17:32:04 -0400
f17bb68b01 New Verilog pbrazzle 2022-09-21 17:22:54 -0400
6b811d60cf New Verilog pbrazzle 2022-09-21 17:05:08 -0400
8d0740106d New Verilog pbrazzle 2022-09-21 16:52:25 -0400
791fe825a0 New Verilog pbrazzle 2022-09-21 16:43:54 -0400
19416a30c3 New Verilog pbrazzle 2022-09-21 16:32:26 -0400
b4b3c1d8e3 New Verilog pbrazzle 2022-09-21 10:06:07 -0400
72e99aaa51 New Verilog pbrazzle 2022-09-21 09:57:45 -0400
5d17242354 New Verilog pbrazzle 2022-09-21 09:05:13 -0400
18387e325f New Verilog pbrazzle 2022-09-21 09:01:41 -0400
fa33b94fb3 New Verilog pbrazzle 2022-09-21 08:59:40 -0400
f2dcd2e28d New Verilog pbrazzle 2022-09-21 08:58:00 -0400
fa6cbc571e New Verilog pbrazzle 2022-09-21 08:56:07 -0400
a5107aec8f New Verilog pbrazzle 2022-09-21 08:41:27 -0400
6f42bc9112

Merge pull request #44 from antmicro/sub_channels_support Maciej Dudek 2022-09-20 18:28:26 +0300
f744a2ff02 Add verilator tests with subchannels enabled Maciej Dudek 2022-09-20 17:06:08 +0200
a78b56dada Update regresion tests with alert_n support Maciej Dudek 2022-09-02 11:25:46 +0200
b1b70f099c Add sub-channels support for ddr5 Maciej Dudek 2022-09-20 14:00:34 +0200
27614e717c

Merge pull request #41 from antmicro/msieron/test-matrix Maciej Dudek 2022-09-20 14:53:40 +0300
a82e1014fe New Verilog pbrazzle 2022-09-19 10:57:06 -0400
9ebea4325e New Verilog pbrazzle 2022-09-19 10:47:17 -0400
f569edf81a New Verilog pbrazzle 2022-09-19 10:37:53 -0400
14a9a8e219 New Verilog pbrazzle 2022-09-16 13:05:49 -0400
031e8a6fad New Verilog pbrazzle 2022-09-16 12:53:02 -0400
a36c6e2f29 New Verilog pbrazzle 2022-09-16 12:43:44 -0400
3e2296e822 New Verilog pbrazzle 2022-09-16 12:34:38 -0400
5d355f52da New Verilog pbrazzle 2022-09-16 12:28:05 -0400
96916f797c New Verilog pbrazzle 2022-09-16 11:56:45 -0400
0d1b2c406c New Verilog pbrazzle 2022-09-16 11:46:28 -0400
4d32cf69f7 New Verilog pbrazzle 2022-09-16 10:56:19 -0400
ccbeafc068 New Verilog pbrazzle 2022-09-16 10:42:47 -0400
15bda74014 New Verilog pbrazzle 2022-09-16 10:30:58 -0400
1b9e7e88e0 New Verilog pbrazzle 2022-09-16 10:21:29 -0400
adf41a8956 New Verilog pbrazzle 2022-09-16 09:59:37 -0400
9f11a7676d New Verilog pbrazzle 2022-09-16 08:23:50 -0400