Florent Kermarrec 05d3be476c phy/ecp5ddrphy: Reduce rdly to 3-bit.		2022-03-22 17:08:51 +01:00
..
core	core/refresher: Add assert on clk_freq/tREFI ratio.	2021-11-01 14:58:41 +01:00
frontend	frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled).	2022-02-28 18:45:46 +01:00
phy	phy/ecp5ddrphy: Reduce rdly to 3-bit.	2022-03-22 17:08:51 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Merge pull request #270 from antmicro/jboc/lpddr5-rebase	2021-11-01 22:18:38 +01:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	litedram_gen: Enable Read-Modify-Write support with ECC.	2022-02-28 18:52:32 +01:00
init.py	init: ddr4: add inversion also in python init	2022-03-02 14:33:51 +01:00
modules.py	add support for MT41K256M8 module	2021-12-20 11:52:11 +08:00