406 lines
18 KiB
Python
406 lines
18 KiB
Python
# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMNativePort, LiteDRAMNativeWritePort, LiteDRAMNativeReadPort
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from litedram.frontend.adapter import LiteDRAMNativePortConverter, LiteDRAMNativePortCDC
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from test.common import *
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from litex.gen.sim import *
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class ConverterDUT(Module):
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def __init__(self, user_data_width, native_data_width, mem_depth, separate_rw=True, read_latency=0):
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self.separate_rw = separate_rw
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if separate_rw:
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self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=user_data_width)
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self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=native_data_width)
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self.read_user_port = LiteDRAMNativeReadPort( address_width=32, data_width=user_data_width)
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self.read_crossbar_port = LiteDRAMNativeReadPort( address_width=32, data_width=native_data_width)
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self.write_driver = NativePortDriver(self.write_user_port)
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self.read_driver = NativePortDriver(self.read_user_port)
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else:
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self.write_user_port = LiteDRAMNativePort(mode="both", address_width=32, data_width=user_data_width)
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self.write_crossbar_port = LiteDRAMNativePort(mode="both", address_width=32, data_width=native_data_width)
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self.write_driver = NativePortDriver(self.write_user_port)
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self.read_user_port = self.write_user_port
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self.read_crossbar_port = self.write_crossbar_port
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self.read_driver = self.write_driver
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self.driver_generators = [self.write_driver.write_data_handler(),
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self.read_driver.read_data_handler(latency=read_latency)]
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# Memory
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self.memory = DRAMMemory(native_data_width, mem_depth)
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def do_finalize(self):
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if self.separate_rw:
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self.submodules.write_converter = LiteDRAMNativePortConverter(
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self.write_user_port, self.write_crossbar_port)
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self.submodules.read_converter = LiteDRAMNativePortConverter(
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self.read_user_port, self.read_crossbar_port)
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else:
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self.submodules.converter = LiteDRAMNativePortConverter(
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self.write_user_port, self.write_crossbar_port)
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def read(self, address, **kwargs):
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return (yield from self.read_driver.read(address, **kwargs))
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def write(self, address, data, **kwargs):
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if self.write_user_port.data_width > self.write_crossbar_port.data_width:
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kwargs["data_with_cmd"] = True
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return (yield from self.write_driver.write(address, data, **kwargs))
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class CDCDUT(ConverterDUT):
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def do_finalize(self):
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# Change clock domains
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self.write_user_port.clock_domain = "user"
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self.read_user_port.clock_domain = "user"
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self.write_crossbar_port.clock_domain = "native"
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self.read_crossbar_port.clock_domain = "native"
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# Add CDC
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self.submodules.write_converter = LiteDRAMNativePortCDC(
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port_from = self.write_user_port,
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port_to = self.write_crossbar_port)
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self.submodules.read_converter = LiteDRAMNativePortCDC(
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port_from = self.read_user_port,
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port_to = self.read_crossbar_port)
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class TestAdapter(MemoryTestDataMixin, unittest.TestCase):
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def test_down_converter_ratio_must_be_integer(self):
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with self.assertRaises(ValueError) as cm:
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dut = ConverterDUT(user_data_width=64, native_data_width=24, mem_depth=128)
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dut.finalize()
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self.assertIn("ratio must be an int", str(cm.exception).lower())
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def test_up_converter_ratio_must_be_integer(self):
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with self.assertRaises(ValueError) as cm:
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dut = ConverterDUT(user_data_width=32, native_data_width=48, mem_depth=128)
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dut.finalize()
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self.assertIn("ratio must be an int", str(cm.exception).lower())
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def converter_readback_test(self, dut, pattern, mem_expected, main_generator=None):
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assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!"
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if main_generator is None:
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def main_generator(dut):
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for adr, data in pattern:
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yield from dut.write(adr, data)
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for adr, _ in pattern[:-1]:
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yield from dut.read(adr, wait_data=False)
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# use cmd.last to indicate last command in the sequence
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# this is needed for the cases in up-converter when it cannot be deduced
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# that port_to.cmd should be sent
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adr, _ = pattern[-1]
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yield from dut.read(adr, wait_data=False, last=1)
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yield from dut.write_driver.wait_all()
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yield from dut.read_driver.wait_all()
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generators = [
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main_generator(dut),
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*dut.driver_generators,
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.read_handler(dut.read_crossbar_port),
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timeout_generator(1000),
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]
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run_simulation(dut, generators, vcd_name='sim.vcd')
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self.assertEqual(dut.memory.mem, mem_expected)
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self.assertEqual(dut.read_driver.rdata, [data for adr, data in pattern])
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def converter_test(self, test_data, user_data_width, native_data_width, **kwargs):
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for separate_rw in [True, False]:
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with self.subTest(separate_rw=separate_rw):
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data = self.pattern_test_data[test_data]
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dut = ConverterDUT(user_data_width=user_data_width, native_data_width=native_data_width,
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mem_depth=len(data["expected"]), separate_rw=separate_rw, **kwargs)
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self.converter_readback_test(dut, data["pattern"], data["expected"])
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def test_converter_1to1(self):
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# Verify 64-bit to 64-bit identify-conversion.
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self.converter_test(test_data="64bit", user_data_width=64, native_data_width=64)
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def test_converter_2to1(self):
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# Verify 64-bit to 32-bit down-conversion.
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self.converter_test(test_data="64bit_to_32bit", user_data_width=64, native_data_width=32)
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def test_converter_4to1(self):
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# Verify 32-bit to 8-bit down-conversion.
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self.converter_test(test_data="32bit_to_8bit", user_data_width=32, native_data_width=8)
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def test_converter_8to1(self):
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# Verify 64-bit to 8-bit down-conversion.
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self.converter_test(test_data="64bit_to_8bit", user_data_width=64, native_data_width=8)
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def test_converter_1to2(self):
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# Verify 8-bit to 16-bit up-conversion.
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self.converter_test(test_data="8bit_to_16bit", user_data_width=8, native_data_width=16)
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def test_converter_1to4(self):
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# Verify 32-bit to 128-bit up-conversion.
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self.converter_test(test_data="32bit_to_128bit", user_data_width=32, native_data_width=128)
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def test_converter_1to8(self):
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# Verify 32-bit to 256-bit up-conversion.
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self.converter_test(test_data="32bit_to_256bit", user_data_width=32, native_data_width=256)
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def test_up_converter_read_latencies(self):
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# Verify that up-conversion works with different port reader latencies
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cases = {
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"1to2": dict(test_data="8bit_to_16bit", user_data_width=8, native_data_width=16),
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"1to4": dict(test_data="32bit_to_128bit", user_data_width=32, native_data_width=128),
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"1to8": dict(test_data="32bit_to_256bit", user_data_width=32, native_data_width=256),
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}
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for latency in [0, 1]:
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with self.subTest(latency=latency):
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for conversion, kwargs in cases.items():
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with self.subTest(conversion=conversion):
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self.converter_test(**kwargs, read_latency=latency)
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def test_down_converter_read_latencies(self):
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# Verify that down-conversion works with different port reader latencies
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cases = {
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"2to1": dict(test_data="64bit_to_32bit", user_data_width=64, native_data_width=32),
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"4to1": dict(test_data="32bit_to_8bit", user_data_width=32, native_data_width=8),
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"8to1": dict(test_data="64bit_to_8bit", user_data_width=64, native_data_width=8),
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}
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for latency in [0, 1]:
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with self.subTest(latency=latency):
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for conversion, kwargs in cases.items():
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with self.subTest(conversion=conversion):
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self.converter_test(**kwargs, read_latency=latency)
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def test_up_converter_write_complete_sequence(self):
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# Verify up-conversion when master sends full sequences (of `ratio` length)
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def main_generator(dut):
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yield from dut.write(0x00, 0x11) # first
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yield from dut.write(0x01, 0x22)
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yield from dut.write(0x02, 0x33)
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yield from dut.write(0x03, 0x44)
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yield from dut.write(0x04, 0x55) # second
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yield from dut.write(0x05, 0x66)
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yield from dut.write(0x06, 0x77)
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yield from dut.write(0x07, 0x88)
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yield from dut.write_driver.wait_all()
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for _ in range(8): # wait for memory
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yield
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mem_expected = [
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# data address
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0x44332211, # 0x00
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0x88776655, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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]
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for separate_rw in [True, False]:
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with self.subTest(separate_rw=separate_rw):
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(mem_expected), separate_rw=separate_rw)
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self.converter_readback_test(dut, pattern=[], mem_expected=mem_expected,
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main_generator=main_generator)
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def test_up_converter_write_with_manual_flush(self):
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# Verify that up-conversion writes incomplete data when it receives cmd.last
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def main_generator(dut):
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yield from dut.write(0x00, 0x11, wait_data=False)
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yield from dut.write(0x01, 0x22, wait_data=False)
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yield from dut.write(0x02, 0x33, wait_data=False, last=1)
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yield from dut.write_driver.wait_all()
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for _ in range(8): # wait for memory
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yield
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mem_expected = [
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# data address
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0x00332211, # 0x00
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0x00000000, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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]
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for separate_rw in [True, False]:
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with self.subTest(separate_rw=separate_rw):
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(mem_expected), separate_rw=separate_rw)
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self.converter_readback_test(dut, pattern=[], mem_expected=mem_expected,
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main_generator=main_generator)
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def test_up_converter_auto_flush_on_address_change(self):
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# Verify that up-conversion automatically flushes the cmd if the (shifted) address changes
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def main_generator(dut):
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yield from dut.write(0x00, 0x11, wait_data=False) # -> 0x00
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yield from dut.write(0x01, 0x22, wait_data=False) # -> 0x00
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yield from dut.write(0x02, 0x33, wait_data=False) # -> 0x00
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yield from dut.write(0x04, 0x55, wait_data=False) # -> 0x01
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yield from dut.write(0x05, 0x66, wait_data=False) # -> 0x01
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yield from dut.write(0x06, 0x77, wait_data=False) # -> 0x01
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yield from dut.write(0x07, 0x88, wait_data=False) # -> 0x01
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yield from dut.write_driver.wait_all()
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for _ in range(8): # wait for memory
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yield
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mem_expected = [
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# data address
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0x00332211, # 0x00
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0x88776655, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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]
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for separate_rw in [True, False]:
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with self.subTest(separate_rw=separate_rw):
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(mem_expected), separate_rw=separate_rw)
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self.converter_readback_test(dut, pattern=[], mem_expected=mem_expected,
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main_generator=main_generator)
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def test_up_converter_auto_flush_on_cmd_we_change(self):
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# Verify that up-conversion automatically flushes the cmd when command type (write/read) changes
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def main_generator(dut):
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yield from dut.write(0x00, 0x11, wait_data=False)
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yield from dut.write(0x01, 0x22, wait_data=False)
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yield from dut.read(0x00, wait_data=False)
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yield from dut.read(0x01, wait_data=False)
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yield from dut.read(0x02, wait_data=False)
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yield from dut.read(0x03, wait_data=False)
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yield from dut.write_driver.wait_all()
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yield from dut.read_driver.wait_all()
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for _ in range(8): # wait for memory
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yield
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mem_expected = [
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# data address
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0x00002211, # 0x00
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0x00000000, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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]
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pattern = [
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(0x00, 0x11),
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(0x01, 0x22),
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(0x02, 0x00),
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(0x03, 0x00),
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]
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# with separate_rw=True we will fail because read will happen before write completes
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(mem_expected), separate_rw=False)
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self.converter_readback_test(dut, pattern=pattern, mem_expected=mem_expected,
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main_generator=main_generator)
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def test_up_converter_write_with_gap(self):
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# Verify that the up-converter can mask data properly when sending non-sequential writes
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def main_generator(dut):
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yield from dut.write(0x00, 0x11, wait_data=False)
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yield from dut.write(0x02, 0x22, wait_data=False)
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yield from dut.write(0x03, 0x33, wait_data=False, last=1)
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yield from dut.write_driver.wait_all()
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for _ in range(8): # wait for memory
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yield
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mem_expected = [
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# data, address
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0x33220011, # 0x00
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0x00000000, # 0x04
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0x00000000, # 0x08
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0x00000000, # 0x0c
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]
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for separate_rw in [True, False]:
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with self.subTest(separate_rw=separate_rw):
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(mem_expected), separate_rw=separate_rw)
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self.converter_readback_test(dut, pattern=[], mem_expected=mem_expected,
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main_generator=main_generator)
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def test_up_converter_not_aligned(self):
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data = self.pattern_test_data["8bit_to_32bit_not_aligned"]
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dut = ConverterDUT(user_data_width=8, native_data_width=32,
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mem_depth=len(data["expected"]), separate_rw=False)
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self.converter_readback_test(dut, data["pattern"], data["expected"])
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def cdc_readback_test(self, dut, pattern, mem_expected, clocks):
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assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!"
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read_data = []
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@passive
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def read_handler(read_port):
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yield read_port.rdata.ready.eq(1)
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while True:
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if (yield read_port.rdata.valid):
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read_data.append((yield read_port.rdata.data))
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yield
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def main_generator(dut, pattern):
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for adr, data in pattern:
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yield from dut.write(adr, data)
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for adr, _ in pattern:
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yield from dut.read(adr, wait_data=False)
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yield from dut.write_driver.wait_all()
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yield from dut.read_driver.wait_all()
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generators = {
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"user": [
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main_generator(dut, pattern),
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read_handler(dut.read_user_port),
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*dut.driver_generators,
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timeout_generator(5000),
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],
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"native": [
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dut.memory.write_handler(dut.write_crossbar_port),
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dut.memory.read_handler(dut.read_crossbar_port),
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],
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}
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run_simulation(dut, generators, clocks)
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self.assertEqual(dut.memory.mem, mem_expected)
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self.assertEqual(read_data, [data for adr, data in pattern])
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def test_port_cdc_same_clocks(self):
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# Verify CDC with same clocks (frequency and phase).
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data = self.pattern_test_data["32bit"]
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dut = CDCDUT(user_data_width=32, native_data_width=32, mem_depth=len(data["expected"]))
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clocks = {
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"user": 10,
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"native": (7, 3),
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}
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self.cdc_readback_test(dut, data["pattern"], data["expected"], clocks=clocks)
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def test_port_cdc_different_period(self):
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# Verify CDC with different clock frequencies.
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data = self.pattern_test_data["32bit"]
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dut = CDCDUT(user_data_width=32, native_data_width=32, mem_depth=len(data["expected"]))
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clocks = {
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"user": 10,
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"native": 7,
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}
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self.cdc_readback_test(dut, data["pattern"], data["expected"], clocks=clocks)
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def test_port_cdc_out_of_phase(self):
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# Verify CDC with different clock phases.
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data = self.pattern_test_data["32bit"]
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dut = CDCDUT(user_data_width=32, native_data_width=32, mem_depth=len(data["expected"]))
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clocks = {
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"user": 10,
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"native": (7, 3),
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}
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self.cdc_readback_test(dut, data["pattern"], data["expected"], clocks=clocks)
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