425 lines
16 KiB
Python
425 lines
16 KiB
Python
# This file is Copyright (c) 2016-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import unittest
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from migen import *
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from litex.gen.sim import *
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from litedram.common import *
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from litedram.frontend.bist import *
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from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker, \
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_LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
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from test.common import *
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class GenCheckDriver:
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def __init__(self, module):
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self.module = module
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def reset(self):
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yield self.module.reset.eq(1)
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yield
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yield self.module.reset.eq(0)
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yield
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def configure(self, base, length, end=None, random_addr=None, random_data=None):
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# for non-pattern generators/checkers
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if end is None:
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end = base + 0x100000
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yield self.module.base.eq(base)
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yield self.module.end.eq(end)
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yield self.module.length.eq(length)
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if random_addr is not None:
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yield self.module.random_addr.eq(random_addr)
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if random_data is not None:
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yield self.module.random_data.eq(random_data)
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def run(self):
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yield self.module.run.eq(1)
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yield self.module.start.eq(1)
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yield
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yield self.module.start.eq(0)
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yield
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while((yield self.module.done) == 0):
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yield
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if hasattr(self.module, "errors"):
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self.errors = (yield self.module.errors)
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class GenCheckCSRDriver:
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def __init__(self, module):
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self.module = module
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def reset(self):
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yield from self.module.reset.write(1)
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yield from self.module.reset.write(0)
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def configure(self, base, length, end=None, random_addr=None, random_data=None):
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# for non-pattern generators/checkers
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if end is None:
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end = base + 0x100000
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yield from self.module.base.write(base)
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yield from self.module.end.write(end)
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yield from self.module.length.write(length)
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if random_addr is not None:
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yield from self.module.random.addr.write(random_addr)
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if random_data is not None:
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yield from self.module.random.data.write(random_data)
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def run(self):
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yield from self.module.run.write(1)
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yield from self.module.start.write(1)
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yield
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yield from self.module.start.write(0)
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yield
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while((yield from self.module.done.read()) == 0):
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yield
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if hasattr(self.module, "errors"):
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self.errors = (yield from self.module.errors.read())
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class TestBIST(MemoryTestDataMixin, unittest.TestCase):
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# Generator ------------------------------------------------------------------------------------
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def test_generator(self):
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def main_generator(dut):
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self.errors = 0
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# test incr
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(0)
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yield
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for i in range(1024):
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data = (yield dut.o)
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if data != i:
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self.errors += 1
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yield
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# test random
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datas = []
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yield dut.ce.eq(1)
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yield dut.random_enable.eq(1)
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for i in range(1024):
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data = (yield dut.o)
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if data in datas:
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self.errors += 1
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datas.append(data)
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yield
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# dut
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dut = Generator(23, n_state=23, taps=[17, 22])
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# simulation
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generators = [main_generator(dut)]
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run_simulation(dut, generators)
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self.assertEqual(self.errors, 0)
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def generator_test(self, mem_expected, data_width, pattern=None, config_args=None,
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check_mem=True):
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assert pattern is None or config_args is None, \
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"_LiteDRAMBISTGenerator xor _LiteDRAMPatternGenerator"
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=data_width)
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if pattern is not None:
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self.submodules.generator = _LiteDRAMPatternGenerator(self.write_port, pattern)
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else:
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port)
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self.mem = DRAMMemory(data_width, len(mem_expected))
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def main_generator(driver):
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yield from driver.reset()
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if pattern is None:
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yield from driver.configure(**config_args)
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yield from driver.run()
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yield
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dut = DUT()
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generators = [
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main_generator(GenCheckDriver(dut.generator)),
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dut.mem.write_handler(dut.write_port),
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]
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run_simulation(dut, generators)
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if check_mem:
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self.assertEqual(dut.mem.mem, mem_expected)
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return dut
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# _LiteDRAMBISTGenerator -----------------------------------------------------------------------
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def test_bist_generator_8bit(self):
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data = self.bist_test_data["8bit"]
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self.generator_test(data.pop("expected"), data_width=8, config_args=data)
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def test_bist_generator_range_must_be_pow2(self):
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# NOTE:
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# in the current implementation (end - start) must be a power of 2,
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# but it would be better if this restriction didn't hold, this test
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# is here just to notice the change if it happens unintentionally
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# and may be removed if we start supporting arbitrary ranges
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data = self.bist_test_data["8bit"]
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data["end"] += 1
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reference = data.pop("expected")
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dut = self.generator_test(reference, data_width=8, config_args=data, check_mem=False)
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self.assertNotEqual(dut.mem.mem, reference)
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def test_bist_generator_32bit(self):
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data = self.bist_test_data["32bit"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_64bit(self):
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data = self.bist_test_data["64bit"]
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self.generator_test(data.pop("expected"), data_width=64, config_args=data)
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def test_bist_generator_32bit_address_masked(self):
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data = self.bist_test_data["32bit_masked"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_32bit_long_sequential(self):
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data = self.bist_test_data["32bit_long_sequential"]
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self.generator_test(data.pop("expected"), data_width=32, config_args=data)
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def test_bist_generator_random_data(self):
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data = self.bist_test_data["32bit"]
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data["random_data"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data,
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check_mem=False)
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# only check that there are no duplicates and that data is not a simple sequence
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mem = [val for val in dut.mem.mem if val != 0]
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self.assertEqual(len(set(mem)), len(mem), msg="Duplicate values in memory")
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self.assertNotEqual(mem, list(range(len(mem))), msg="Values are a sequence")
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def test_bist_generator_random_addr(self):
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data = self.bist_test_data["32bit"]
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data["random_addr"] = True
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dut = self.generator_test(data.pop("expected"), data_width=32, config_args=data,
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check_mem=False)
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# with random address and address wrapping (generator.end) we _can_ have duplicates
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# we can at least check that the values written are not an ordered sequence
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mem = [val for val in dut.mem.mem if val != 0]
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self.assertNotEqual(mem, list(range(len(mem))), msg="Values are a sequence")
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self.assertLess(max(mem), data["length"], msg="Too big value found")
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# _LiteDRAMPatternGenerator --------------------------------------------------------------------
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def test_pattern_generator_8bit(self):
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data = self.pattern_test_data["8bit"]
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self.generator_test(data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_generator_32bit(self):
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data = self.pattern_test_data["32bit"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_64bit(self):
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data = self.pattern_test_data["64bit"]
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self.generator_test(data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_generator_32bit_not_aligned(self):
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data = self.pattern_test_data["32bit_not_aligned"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_duplicates(self):
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data = self.pattern_test_data["32bit_duplicates"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_generator_32bit_sequential(self):
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data = self.pattern_test_data["32bit_sequential"]
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self.generator_test(data["expected"], data_width=32, pattern=data["pattern"])
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# _LiteDRAMBISTChecker -------------------------------------------------------------------------
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def checker_test(self, memory, data_width, pattern=None, config_args=None, check_errors=False):
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assert pattern is None or config_args is None, \
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"_LiteDRAMBISTChecker xor _LiteDRAMPatternChecker"
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class DUT(Module):
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def __init__(self):
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=data_width)
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if pattern is not None:
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self.submodules.checker = _LiteDRAMPatternChecker(self.read_port, init=pattern)
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else:
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port)
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self.mem = DRAMMemory(data_width, len(memory), init=memory)
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def main_generator(driver):
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yield from driver.reset()
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if pattern is None:
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yield from driver.configure(**config_args)
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yield from driver.run()
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yield
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dut = DUT()
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checker = GenCheckDriver(dut.checker)
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generators = [
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main_generator(checker),
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dut.mem.read_handler(dut.read_port),
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]
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run_simulation(dut, generators)
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if check_errors:
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self.assertEqual(checker.errors, 0)
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return dut, checker
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def test_bist_checker_8bit(self):
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data = self.bist_test_data["8bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=8, config_args=data)
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def test_bist_checker_32bit(self):
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data = self.bist_test_data["32bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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def test_bist_checker_64bit(self):
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data = self.bist_test_data["32bit"]
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memory = data.pop("expected")
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self.checker_test(memory, data_width=32, config_args=data)
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# _LiteDRAMPatternChecker ----------------------------------------------------------------------
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def test_pattern_checker_8bit(self):
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data = self.pattern_test_data["8bit"]
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self.checker_test(memory=data["expected"], data_width=8, pattern=data["pattern"])
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def test_pattern_checker_32bit(self):
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data = self.pattern_test_data["32bit"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_64bit(self):
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data = self.pattern_test_data["64bit"]
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self.checker_test(memory=data["expected"], data_width=64, pattern=data["pattern"])
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def test_pattern_checker_32bit_not_aligned(self):
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data = self.pattern_test_data["32bit_not_aligned"]
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self.checker_test(memory=data["expected"], data_width=32, pattern=data["pattern"])
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def test_pattern_checker_32bit_duplicates(self):
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data = self.pattern_test_data["32bit_duplicates"]
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num_duplicates = len(data["pattern"]) - len(set(adr for adr, _ in data["pattern"]))
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dut, checker = self.checker_test(
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memory=data["expected"], data_width=32, pattern=data["pattern"], check_errors=False)
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self.assertEqual(checker.errors, num_duplicates)
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# LiteDRAMBISTGenerator and LiteDRAMBISTChecker ------------------------------------------------
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def bist_test(self, generator, checker, mem):
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# write
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yield from generator.reset()
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yield from generator.configure(16, 64)
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yield from generator.run()
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# read (no errors)
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yield from checker.reset()
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yield from checker.configure(16, 64)
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yield from checker.run()
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self.assertEqual(checker.errors, 0)
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# corrupt memory (using generator)
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yield from generator.reset()
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yield from generator.configure(16 + 48, 64)
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yield from generator.run()
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# read (errors)
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yield from checker.reset()
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yield from checker.configure(16, 64)
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yield from checker.run()
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# errors for words:
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# from (16 + 48) / 4 = 16 (corrupting generator start)
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# to (16 + 64) / 4 = 20 (first generator end)
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self.assertEqual(checker.errors, 4)
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# read (no errors)
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yield from checker.reset()
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yield from checker.configure(16 + 48, 64)
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yield from checker.run()
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self.assertEqual(checker.errors, 0)
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def test_bist_base(self):
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port)
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def main_generator(dut, mem):
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generator = GenCheckDriver(dut.generator)
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checker = GenCheckDriver(dut.checker)
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yield from self.bist_test(generator, checker, mem)
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# dut
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dut = DUT()
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mem = DRAMMemory(32, 48)
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# simulation
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generators = [
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main_generator(dut, mem),
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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run_simulation(dut, generators)
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def test_bist_csr(self):
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class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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def main_generator(dut, mem):
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generator = GenCheckCSRDriver(dut.generator)
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checker = GenCheckCSRDriver(dut.checker)
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yield from self.bist_test(generator, checker, mem)
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# dut
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dut = DUT()
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mem = DRAMMemory(32, 48)
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# simulation
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generators = [
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main_generator(dut, mem),
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mem.write_handler(dut.write_port),
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mem.read_handler(dut.read_port)
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]
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run_simulation(dut, generators)
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# FIXME: synchronization between CSRs: `start` and `base`, `done` and `errors`
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# def test_bist_csr_cdc(self):
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# class DUT(Module):
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# def __init__(self):
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# port_kwargs = dict(address_width=32, data_width=32, clock_domain="async")
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# self.write_port = LiteDRAMNativeWritePort(**port_kwargs)
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# self.read_port = LiteDRAMNativeReadPort(**port_kwargs)
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# self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
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# self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
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#
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# def main_generator(dut, mem):
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# generator = GenCheckCSRDriver(dut.generator)
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# checker = GenCheckCSRDriver(dut.checker)
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# yield from self.bist_test(generator, checker, mem)
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#
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# # dut
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# dut = DUT()
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# mem = DRAMMemory(32, 48)
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#
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# generators = {
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# "sys": [
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# main_generator(dut, mem),
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# ],
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# "async": [
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# mem.write_handler(dut.write_port),
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# mem.read_handler(dut.read_port)
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# ]
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# }
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# clocks = {
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# "sys": 10,
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# "async": (7, 3),
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# }
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# run_simulation(dut, generators, clocks)
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