56 lines
1.8 KiB
Python
56 lines
1.8 KiB
Python
from migen.fhdl.std import *
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from migen.sim.generic import run_simulation
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from litedram.common import *
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from litedram.modules import MT48LC4M16
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from litedram.core.bankmachine import LiteDRAMBankMachine
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from test.common import *
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class CmdGen(Module):
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def __init__(self, dram_module):
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self.rowbits = rowbits = dram_module.geom_settings.rowbits
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self.colbits = colbits = dram_module.geom_settings.colbits
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self.cmd = Source(dram_cmd_description(rowbits, colbits))
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self.n = 0
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def do_simulation(self, selfp):
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if selfp.cmd.ack:
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if self.n < 100:
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selfp.cmd.stb = 1
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selfp.cmd.row = randn(2**self.rowbits-1)
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selfp.cmd.col = randn(2**self.colbits-1)
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self.n += 1
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else:
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selfp.cmd.stb = 0
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class TB(Module):
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def __init__(self):
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dram_module = MT48LC4M16(100*1000000)
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self.submodules.bankmachine = LiteDRAMBankMachine(dram_module, 16)
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self.submodules.write_gen = CmdGen(dram_module)
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self.submodules.read_gen = CmdGen(dram_module)
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self.comb += [
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Record.connect(self.write_gen.cmd, self.bankmachine.write_cmd),
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Record.connect(self.read_gen.cmd, self.bankmachine.read_cmd),
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self.bankmachine.cmd.ack.eq(1)
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]
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self.nreads = 0
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self.nwrites = 0
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def do_simulation(self, selfp):
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if selfp.bankmachine.cmd.stb:
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if selfp.bankmachine.cmd.write:
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self.nwrites += 1
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print("nwrites {}/ nreads {}".format(self.nwrites, self.nreads))
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elif selfp.bankmachine.cmd.read:
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self.nreads += 1
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print("nwrites {}/ nreads {}".format(self.nwrites, self.nreads))
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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