574 lines
20 KiB
Python
574 lines
20 KiB
Python
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import copy
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import random
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import unittest
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from collections import namedtuple
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from migen import *
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from litex.soc.interconnect import stream
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from litedram.common import *
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from litedram.phy import dfi
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from litedram.core.multiplexer import Multiplexer
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# load after "* imports" to avoid using Migen version of vcd.py
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from litex.gen.sim import run_simulation
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from test.common import timeout_generator, CmdRequestRWDriver
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def dfi_cmd_to_char(cas_n, ras_n, we_n):
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return {
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(1, 1, 1): "_",
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(0, 1, 0): "w",
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(0, 1, 1): "r",
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(1, 0, 1): "a",
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(1, 0, 0): "p",
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(0, 0, 1): "f",
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}[(cas_n, ras_n, we_n)]
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class BankMachineStub:
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def __init__(self, babits, abits):
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self.cmd = stream.Endpoint(cmd_request_rw_layout(a=abits, ba=babits))
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self.refresh_req = Signal()
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self.refresh_gnt = Signal()
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class RefresherStub:
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def __init__(self, babits, abits):
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self.cmd = stream.Endpoint(cmd_request_rw_layout(a=abits, ba=babits))
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class MultiplexerDUT(Module):
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# define default settings that can be overwritten in specific tests
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# use only these settings that we actually need for Multiplexer
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default_controller_settings = dict(
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read_time=32,
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write_time=16,
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with_bandwidth=False,
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)
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default_phy_settings = dict(
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nphases=2,
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rdphase=0,
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wrphase=1,
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rdcmdphase=1,
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wrcmdphase=0,
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read_latency=5,
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cwl=3,
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# indirectly
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nranks=1,
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databits=16,
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dfi_databits=2*16,
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memtype="DDR2",
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)
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default_geom_settings = dict(
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bankbits=3,
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rowbits=13,
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colbits=10,
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)
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default_timing_settings = dict(
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tWTR=2,
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tFAW=None,
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tCCD=1,
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tRRD=None,
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)
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def __init__(self, controller_settings=None, phy_settings=None, geom_settings=None,
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timing_settings=None):
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# update settings if provided
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def updated(settings, update):
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copy = settings.copy()
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copy.update(update or {})
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return copy
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controller_settings = updated(self.default_controller_settings, controller_settings)
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phy_settings = updated(self.default_phy_settings, phy_settings)
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geom_settings = updated(self.default_geom_settings, geom_settings)
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timing_settings = updated(self.default_timing_settings, timing_settings)
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# use simpler settigns to include only Multiplexer-specific members
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class SimpleSettings(Settings):
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def __init__(self, **kwargs):
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self.set_attributes(kwargs)
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settings = SimpleSettings(**controller_settings)
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settings.phy = SimpleSettings(**phy_settings)
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settings.geom = SimpleSettings(**geom_settings)
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settings.timing = SimpleSettings(**timing_settings)
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settings.geom.addressbits = max(settings.geom.rowbits, settings.geom.colbits)
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self.settings = settings
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# create interfaces and stubs required to instantiate Multiplexer
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abits = settings.geom.addressbits
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babits = settings.geom.bankbits
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nbanks = 2**babits
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nranks = settings.phy.nranks
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self.bank_machines = [BankMachineStub(abits=abits, babits=babits)
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for _ in range(nbanks*nranks)]
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self.refresher = RefresherStub(abits=abits, babits=babits)
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self.dfi = dfi.Interface(addressbits=abits, bankbits=babits, nranks=settings.phy.nranks,
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databits=settings.phy.dfi_databits, nphases=settings.phy.nphases)
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address_align = log2_int(burst_lengths[settings.phy.memtype])
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self.interface = LiteDRAMInterface(address_align=address_align, settings=settings)
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# add Multiplexer
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self.submodules.multiplexer = Multiplexer(settings, self.bank_machines, self.refresher,
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self.dfi, self.interface)
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# add helpers for driving bank machines/refresher
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self.bm_drivers = [CmdRequestRWDriver(bm.cmd, i) for i, bm in enumerate(self.bank_machines)]
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self.refresh_driver = CmdRequestRWDriver(self.refresher.cmd, i=1)
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def fsm_state(self):
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# return name of current state of Multiplexer's FSM
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return self.multiplexer.fsm.decoding[(yield self.multiplexer.fsm.state)]
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class TestMultiplexer(unittest.TestCase):
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def test_init(self):
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# Verify that instantiation of Multiplexer in MultiplexerDUT is correct
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# This will fail if Multiplexer starts using any new setting from controller.settings
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MultiplexerDUT()
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def test_fsm_start_at_read(self):
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# FSM should start at READ state (assumed in some other tests)
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def main_generator(dut):
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self.assertEqual((yield from dut.fsm_state()), "READ")
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dut = MultiplexerDUT()
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run_simulation(dut, main_generator(dut))
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def test_fsm_read_to_write_latency(self):
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# Verify the timing of READ to WRITE transition
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def main_generator(dut):
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rtw = dut.settings.phy.read_latency
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expected = "r" + (rtw - 1) * ">" + "w"
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states = ""
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# set write_available=1
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yield from dut.bm_drivers[0].write()
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yield
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for _ in range(len(expected)):
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state = (yield from dut.fsm_state())
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# use ">" for all other states, as FSM.delayed_enter uses
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# anonymous states instead of staying in RTW
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states += {
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"READ": "r",
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"WRITE": "w",
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}.get(state, ">")
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yield
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self.assertEqual(states, expected)
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dut = MultiplexerDUT()
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run_simulation(dut, main_generator(dut))
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def test_fsm_write_to_read_latency(self):
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# Verify the timing of WRITE to READ transition
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def main_generator(dut):
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write_latency = math.ceil(dut.settings.phy.cwl / dut.settings.phy.nphases)
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wtr = dut.settings.timing.tWTR + write_latency + dut.settings.timing.tCCD or 0
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expected = "w" + (wtr - 1) * ">" + "r"
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states = ""
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# simulate until we are in WRITE
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yield from dut.bm_drivers[0].write()
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while (yield from dut.fsm_state()) != "WRITE":
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yield
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# set read_available=1
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yield from dut.bm_drivers[0].read()
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yield
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for _ in range(len(expected)):
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state = (yield from dut.fsm_state())
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states += {
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"READ": "r",
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"WRITE": "w",
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}.get(state, ">")
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yield
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self.assertEqual(states, expected)
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dut = MultiplexerDUT()
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_steer_read_correct_phases(self):
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# Check that correct phases are being used during READ
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def main_generator(dut):
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yield from dut.bm_drivers[2].read()
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yield from dut.bm_drivers[3].activate()
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while not (yield dut.bank_machines[2].cmd.ready):
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yield
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yield
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# fsm starts in READ
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for phase in range(dut.settings.phy.nphases):
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if phase == dut.settings.phy.rdphase:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 2)
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elif phase == dut.settings.phy.rdcmdphase:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 3)
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else:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 0)
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dut = MultiplexerDUT()
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_steer_write_correct_phases(self):
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# Check that correct phases are being used during WRITE
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def main_generator(dut):
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yield from dut.bm_drivers[2].write()
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yield from dut.bm_drivers[3].activate()
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while not (yield dut.bank_machines[2].cmd.ready):
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yield
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yield
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# fsm starts in READ
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for phase in range(dut.settings.phy.nphases):
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if phase == dut.settings.phy.wrphase:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 2)
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elif phase == dut.settings.phy.wrcmdphase:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 3)
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else:
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self.assertEqual((yield dut.dfi.phases[phase].bank), 0)
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dut = MultiplexerDUT()
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_single_phase_cmd_req(self):
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# Verify that, for a single phase, commands are sent sequentially
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def main_generator(dut):
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yield from dut.bm_drivers[2].write()
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yield from dut.bm_drivers[3].activate()
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ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
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# activate should appear first
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while not ((yield ready[2]) or (yield ready[3])):
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yield
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yield from dut.bm_drivers[3].nop()
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yield
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self.assertEqual((yield dut.dfi.phases[0].bank), 3)
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# than write
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while not (yield ready[2]):
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yield
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yield from dut.bm_drivers[2].nop()
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yield
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self.assertEqual((yield dut.dfi.phases[0].bank), 2)
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dut = MultiplexerDUT(phy_settings=dict(nphases=1))
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_ras_trrd(self):
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# Verify tRRD
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def main_generator(dut):
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yield from dut.bm_drivers[2].activate()
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yield from dut.bm_drivers[3].activate()
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ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
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# wait for activate
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while not ((yield ready[2]) or (yield ready[3])):
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yield
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# invalidate command that was ready
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if (yield ready[2]):
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yield from dut.bm_drivers[2].nop()
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else:
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yield from dut.bm_drivers[3].nop()
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yield
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# wait for the second activate; start from 1 for the previous cycle
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ras_time = 1
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while not ((yield ready[2]) or (yield ready[3])):
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ras_time += 1
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yield
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self.assertEqual(ras_time, 6)
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dut = MultiplexerDUT(timing_settings=dict(tRRD=6))
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_cas_tccd(self):
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# Verify tCCD
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def main_generator(dut):
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yield from dut.bm_drivers[2].read()
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yield from dut.bm_drivers[3].read()
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ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
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# wait for activate
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while not ((yield ready[2]) or (yield ready[3])):
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yield
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# invalidate command that was ready
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if (yield ready[2]):
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yield from dut.bm_drivers[2].nop()
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else:
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yield from dut.bm_drivers[3].nop()
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yield
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# wait for the second activate; start from 1 for the previous cycle
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cas_time = 1
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while not ((yield ready[2]) or (yield ready[3])):
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cas_time += 1
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yield
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self.assertEqual(cas_time, 3)
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dut = MultiplexerDUT(timing_settings=dict(tCCD=3))
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_fsm_anti_starvation(self):
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# Check that anti-starvation works according to controller settings
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def main_generator(dut):
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yield from dut.bm_drivers[2].read()
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yield from dut.bm_drivers[3].write()
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# go to WRITE
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# anti starvation does not work for 1st read, as read_time_en already starts as 1
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# READ -> RTW -> WRITE
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while (yield from dut.fsm_state()) != "WRITE":
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yield
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# wait for write anti starvation
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for _ in range(dut.settings.write_time):
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self.assertEqual((yield from dut.fsm_state()), "WRITE")
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yield
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self.assertEqual((yield from dut.fsm_state()), "WTR")
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# WRITE -> WTR -> READ
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while (yield from dut.fsm_state()) != "READ":
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yield
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# wait for read anti starvation
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for _ in range(dut.settings.read_time):
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self.assertEqual((yield from dut.fsm_state()), "READ")
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yield
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self.assertEqual((yield from dut.fsm_state()), "RTW")
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dut = MultiplexerDUT()
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generators = [
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main_generator(dut),
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timeout_generator(100),
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]
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run_simulation(dut, generators)
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def test_write_datapath(self):
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# Verify that data is transmitted from native interface to DFI
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def main_generator(dut):
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yield from dut.bm_drivers[2].write()
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# 16bits * 2 (DDR) * 1 (phases)
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yield dut.interface.wdata.eq(0xbaadf00d)
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yield dut.interface.wdata_we.eq(0xf)
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while not (yield dut.bank_machines[2].cmd.ready):
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yield
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yield
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self.assertEqual((yield dut.dfi.phases[0].wrdata), 0xbaadf00d)
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self.assertEqual((yield dut.dfi.phases[0].wrdata_en), 1)
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self.assertEqual((yield dut.dfi.phases[0].address), 2)
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self.assertEqual((yield dut.dfi.phases[0].bank), 2)
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dut = MultiplexerDUT(phy_settings=dict(nphases=1))
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_read_datapath(self):
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# Verify that data is transmitted from DFI to native interface
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def main_generator(dut):
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yield from dut.bm_drivers[2].write()
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# 16bits * 2 (DDR) * 1 (phases)
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yield dut.dfi.phases[0].rddata.eq(0xbaadf00d)
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yield dut.dfi.phases[0].rddata_en.eq(1)
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yield
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while not (yield dut.bank_machines[2].cmd.ready):
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yield
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yield
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self.assertEqual((yield dut.interface.rdata), 0xbaadf00d)
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self.assertEqual((yield dut.interface.wdata_we), 0)
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self.assertEqual((yield dut.dfi.phases[0].address), 2)
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self.assertEqual((yield dut.dfi.phases[0].bank), 2)
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dut = MultiplexerDUT(phy_settings=dict(nphases=1))
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generators = [
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main_generator(dut),
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timeout_generator(50),
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]
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run_simulation(dut, generators)
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def test_refresh_requires_gnt(self):
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# After refresher command request, multiplexer waits for permission from all bank machines
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def main_generator(dut):
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def assert_dfi_cmd(cas, ras, we):
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p = dut.dfi.phases[0]
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cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
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self.assertEqual((cas_n, ras_n, we_n), (1 - cas, 1 - ras, 1 - we))
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for bm in dut.bank_machines:
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self.assertEqual((yield bm.refresh_req), 0)
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yield from dut.refresh_driver.refresh()
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yield
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# bank machines get the request
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for bm in dut.bank_machines:
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self.assertEqual((yield bm.refresh_req), 1)
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# no command yet
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yield from assert_dfi_cmd(cas=0, ras=0, we=0)
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# grant permission for refresh
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prng = random.Random(42)
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delays = [prng.randrange(100) for _ in dut.bank_machines]
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for t in range(max(delays) + 1):
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# grant permission
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for delay, bm in zip(delays, dut.bank_machines):
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if delay == t:
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yield bm.refresh_gnt.eq(1)
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yield
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# make sure thare is no command yet
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yield from assert_dfi_cmd(cas=0, ras=0, we=0)
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yield
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yield
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# refresh command
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yield from assert_dfi_cmd(cas=1, ras=1, we=0)
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dut = MultiplexerDUT()
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run_simulation(dut, main_generator(dut))
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def test_requests_from_multiple_bankmachines(self):
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# Check complex communication scenario with requests from multiple bank machines
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# The communication is greatly simplified - data path is completely ignored,
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# no responses from PHY are simulated. Each bank machine performs a sequence of
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# requests, bank machines are ordered randomly and the DFI command data is
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# checked to verify if all the commands have been sent if correct per-bank order.
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# requests sequence on given bank machines
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bm_sequences = {
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0: "awwwwwwp",
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1: "arrrrrrp",
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2: "arwrwrwp",
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3: "arrrwwwp",
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4: "awparpawp",
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5: "awwparrrrp",
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}
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# convert to lists to use .pop()
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bm_sequences = {bm_num: list(seq) for bm_num, seq in bm_sequences.items()}
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def main_generator(bank_machines, drivers):
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# work on a copy
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bm_seq = copy.deepcopy(bm_sequences)
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def non_empty():
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return list(filter(lambda n: len(bm_seq[n]) > 0, bm_seq.keys()))
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|
# artificially perform the work of LiteDRAMCrossbar by always picking only one request
|
|
prng = random.Random(42)
|
|
while len(non_empty()) > 0:
|
|
# pick random bank machine
|
|
bm_num = prng.choice(non_empty())
|
|
|
|
# set given request
|
|
request_char = bm_seq[bm_num].pop(0)
|
|
yield from drivers[bm_num].request(request_char)
|
|
yield
|
|
|
|
# wait for ready
|
|
while not (yield bank_machines[bm_num].cmd.ready):
|
|
yield
|
|
|
|
# disable it
|
|
yield from drivers[bm_num].nop()
|
|
|
|
for _ in range(16):
|
|
yield
|
|
|
|
# gather data on DFI
|
|
DFISnapshot = namedtuple("DFICapture",
|
|
["cmd", "bank", "address", "wrdata_en", "rddata_en"])
|
|
dfi_snapshots = []
|
|
|
|
@passive
|
|
def dfi_monitor(dfi):
|
|
while True:
|
|
# capture current state of DFI lines
|
|
phases = []
|
|
for i, p in enumerate(dfi.phases):
|
|
# transform cas/ras/we to command name
|
|
cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
|
|
captured = {"cmd": dfi_cmd_to_char(cas_n, ras_n, we_n)}
|
|
|
|
# capture rest of fields
|
|
for field in DFISnapshot._fields:
|
|
if field != "cmd":
|
|
captured[field] = (yield getattr(p, field))
|
|
|
|
phases.append(DFISnapshot(**captured))
|
|
dfi_snapshots.append(phases)
|
|
yield
|
|
|
|
dut = MultiplexerDUT()
|
|
generators = [
|
|
main_generator(dut.bank_machines, dut.bm_drivers),
|
|
dfi_monitor(dut.dfi),
|
|
timeout_generator(200),
|
|
]
|
|
run_simulation(dut, generators)
|
|
|
|
# check captured DFI data with the description
|
|
for snap in dfi_snapshots:
|
|
for i, phase_snap in enumerate(snap):
|
|
if phase_snap.cmd == "_":
|
|
continue
|
|
|
|
# distinguish bank machines by the bank number
|
|
bank = phase_snap.bank
|
|
# find next command for the given bank
|
|
cmd = bm_sequences[bank].pop(0)
|
|
|
|
# check if the captured data is correct
|
|
self.assertEqual(phase_snap.cmd, cmd)
|
|
if cmd in ["w", "r"]:
|
|
# addresses are artificially forced to bank numbers in drivers
|
|
self.assertEqual(phase_snap.address, bank)
|
|
if cmd == "w":
|
|
self.assertEqual(phase_snap.wrdata_en, 1)
|
|
if cmd == "r":
|
|
self.assertEqual(phase_snap.rddata_en, 1)
|