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1652ab95c8
litedram
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examples
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Florent Kermarrec
1652ab95c8
examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
2018-09-05 09:13:47 +02:00
..
arty_config.py
add examples with standalone cores for arty and genesys2
2018-08-31 23:20:47 +02:00
genesys2_config.py
add examples with standalone cores for arty and genesys2
2018-08-31 23:20:47 +02:00
litedram_gen.py
examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
2018-09-05 09:13:47 +02:00