94 lines
2.7 KiB
Python
Executable File
94 lines
2.7 KiB
Python
Executable File
import unittest
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort
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from litedram.frontend.adaptation import LiteDRAMPortConverter
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from test.common import *
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from litex.gen.sim import *
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class DUT(Module):
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def __init__(self):
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# write port and converter
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self.write_user_port = LiteDRAMWritePort(aw=32, dw=64)
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self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=32)
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write_converter = LiteDRAMPortConverter(self.write_user_port,
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self.write_crossbar_port)
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self.submodules += write_converter
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# read port and converter
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self.read_user_port = LiteDRAMReadPort(aw=32, dw=64)
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self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=32)
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read_converter = LiteDRAMPortConverter(self.read_user_port,
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self.read_crossbar_port)
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self.submodules += read_converter
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# memory
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self.memory = DRAMMemory(32, 128)
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write_data = [seed_to_data(i, nbits=64) for i in range(8)]
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read_data = []
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@passive
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def read_generator(read_port):
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yield read_port.rdata.ready.eq(1)
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while True:
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if (yield read_port.rdata.valid):
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read_data.append((yield read_port.rdata.data))
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yield
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def main_generator(write_port, read_port):
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# write
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for i in range(8):
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yield write_port.cmd.valid.eq(1)
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yield write_port.cmd.we.eq(1)
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yield write_port.cmd.adr.eq(i)
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yield write_port.wdata.valid.eq(1)
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yield write_port.wdata.data.eq(write_data[i])
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yield
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while (yield write_port.cmd.ready) == 0:
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yield
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while (yield write_port.wdata.ready) == 0:
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yield
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yield
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# read
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yield read_port.rdata.ready.eq(1)
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for i in range(8):
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yield read_port.cmd.valid.eq(1)
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yield read_port.cmd.we.eq(0)
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yield read_port.cmd.adr.eq(i)
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yield
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while (yield read_port.cmd.ready) == 0:
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yield
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yield read_port.cmd.valid.eq(0)
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yield
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# latency delay
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for i in range(32):
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yield
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class TestDownConverter(unittest.TestCase):
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def test(self):
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dut = DUT()
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generators = {
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"sys" : [
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main_generator(dut.write_user_port, dut.read_user_port),
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read_generator(dut.read_user_port),
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dut.memory.write_generator(dut.write_crossbar_port),
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dut.memory.read_generator(dut.read_crossbar_port)
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]
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}
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clocks = {"sys": 10}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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self.assertEqual(write_data, read_data)
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