Florent Kermarrec 6d96bcc1e7 core/bankmachine: fix cas_count size when tccd == 1		2018-07-17 17:41:10 +02:00
..
core	core/bankmachine: fix cas_count size when tccd == 1	2018-07-17 17:41:10 +02:00
frontend	replace litex.gen imports with migen imports	2018-02-23 13:39:23 +01:00
phy	phy/s7ddrphy: add ddr2 support	2018-07-16 09:19:56 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	core/bankmachine: add CAS to CAS support (tCCD)	2018-07-13 15:03:04 +02:00
dfii.py	replace litex.gen imports with migen imports	2018-02-23 13:39:23 +01:00
modules.py	core/bankmachine: add CAS to CAS support (tCCD)	2018-07-13 15:03:04 +02:00