127 lines
4.1 KiB
Verilog
127 lines
4.1 KiB
Verilog
/****************************************************************************************
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*
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* File Name: ddr3_mcp.v
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*
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* Dependencies: ddr3.v, ddr3_parameters.vh
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*
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* Description: Micron SDRAM DDR3 (Double Data Rate 3) multi-chip package model
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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`timescale 1ps / 1ps
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module ddr3_mcp (
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rst_n,
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ck,
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ck_n,
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cke,
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cs_n,
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ras_n,
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cas_n,
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we_n,
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dm_tdqs,
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ba,
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addr,
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dq,
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dqs,
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dqs_n,
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tdqs_n,
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odt
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);
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`ifdef den1024Mb
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`include "1024Mb_ddr3_parameters.vh"
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`elsif den2048Mb
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`include "2048Mb_ddr3_parameters.vh"
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`elsif den4096Mb
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`include "4096Mb_ddr3_parameters.vh"
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`elsif den8192Mb
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`include "8192Mb_ddr3_parameters.vh"
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`else
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// NOTE: Intentionally cause a compile fail here to force the users
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// to select the correct component density before continuing
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ERROR: You must specify component density with +define+den____Mb.
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`endif
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// Declare Ports
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input rst_n;
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input ck;
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input ck_n;
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input [CS_BITS-1:0] cke;
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input [CS_BITS-1:0] cs_n;
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input ras_n;
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input cas_n;
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input we_n;
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inout [DM_BITS-1:0] dm_tdqs;
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input [BA_BITS-1:0] ba;
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input [ADDR_BITS-1:0] addr;
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inout [DQ_BITS-1:0] dq;
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inout [DQS_BITS-1:0] dqs;
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inout [DQS_BITS-1:0] dqs_n;
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output [DQS_BITS-1:0] tdqs_n;
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input [CS_BITS-1:0] odt;
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wire [RANKS-1:0] cke_mcp = cke;
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wire [RANKS-1:0] cs_n_mcp = cs_n;
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wire [RANKS-1:0] odt_mcp = odt;
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function integer ceil;
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input number;
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real number;
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// LMR 4.1.7
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// When either operand of a relational expression is a real operand then the other operand shall be converted
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// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
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if (number > $rtoi(number))
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ceil = $rtoi(number) + 1;
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else
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ceil = number;
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endfunction
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function int max( input int a, b );
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max = (a < b) ? b : a;
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endfunction
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ddr3 rank [RANKS-1:0] (
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rst_n,
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ck,
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ck_n,
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cke_mcp,
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cs_n_mcp,
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ras_n,
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cas_n,
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we_n,
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dm_tdqs,
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ba,
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addr,
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dq,
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dqs,
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dqs_n,
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tdqs_n,
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odt_mcp
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);
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endmodule
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