litedram/litedram
Florent Kermarrec 33f3aa55e5 phy/ecp5ddrphy: add DM remapping capability.
Required on OrangeCrab that has LDM/UDM swapped.
2020-12-16 11:49:33 +01:00
..
core phy/core: move rd/wrcmdphase and computation to Multiplexer. 2020-10-01 11:26:04 +02:00
frontend frontend/bist: expose core for observation. 2020-10-19 09:47:33 +02:00
phy phy/ecp5ddrphy: add DM remapping capability. 2020-12-16 11:49:33 +01:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py common: move cmd/wdata/rdata descriptions and add minimal description of signals. 2020-11-09 12:06:02 +01:00
dfii.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen.py litedram/gen: update LiteDRAMECP5DDRPHYCRG (AsyncResetSynchronizer integrated in PLL). 2020-09-01 13:58:16 +02:00
init.py ddr4: Enable Data Mask for DDR4 memory and invert its polarity. 2020-11-17 15:06:58 +01:00
modules.py modules: remove unnecessary memtypes. 2020-09-01 13:43:09 +02:00