Florent Kermarrec 3586e157f2 frontend/axi: improve len/size comment (-1), set default id_width to 1		2018-11-09 15:29:31 +01:00
..
core	core/bankmachine: typo	2018-10-19 18:20:12 +02:00
frontend	frontend/axi: improve len/size comment (-1), set default id_width to 1	2018-11-09 15:29:31 +01:00
phy	phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering	2018-11-05 17:00:47 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: add DDR4 burst_length	2018-11-05 10:46:34 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: add AS4C256M16D3A	2018-11-08 16:40:38 +01:00
sdram_init.py	sdram_init: fix compilation	2018-11-05 10:46:47 +01:00