127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
#ifndef __GENERATED_SDRAM_PHY_H
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#define __GENERATED_SDRAM_PHY_H
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#include <hw/common.h>
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#include <generated/csr.h>
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#define DFII_CONTROL_SEL 0x01
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#define DFII_CONTROL_CKE 0x02
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#define DFII_CONTROL_ODT 0x04
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#define DFII_CONTROL_RESET_N 0x08
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#define DFII_COMMAND_CS 0x01
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#define DFII_COMMAND_WE 0x02
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#define DFII_COMMAND_CAS 0x04
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#define DFII_COMMAND_RAS 0x08
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#define DFII_COMMAND_WRDATA 0x10
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#define DFII_COMMAND_RDDATA 0x20
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#define SDRAM_PHY_K7DDRPHY
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#define SDRAM_PHY_XDR 2
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#define SDRAM_PHY_DATABITS 64
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#define SDRAM_PHY_PHASES 4
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#define SDRAM_PHY_CL 7
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#define SDRAM_PHY_CWL 6
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#define SDRAM_PHY_CMD_LATENCY 0
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#define SDRAM_PHY_RDPHASE 1
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#define SDRAM_PHY_WRPHASE 2
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#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
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#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
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#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
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#define SDRAM_PHY_READ_LEVELING_CAPABLE
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#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
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#define SDRAM_PHY_DELAYS 32
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#define SDRAM_PHY_BITSLIPS 8
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void cdelay(int i);
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__attribute__((unused)) static inline void command_p0(int cmd)
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{
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sdram_dfii_pi0_command_write(cmd);
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sdram_dfii_pi0_command_issue_write(1);
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}
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__attribute__((unused)) static inline void command_p1(int cmd)
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{
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sdram_dfii_pi1_command_write(cmd);
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sdram_dfii_pi1_command_issue_write(1);
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}
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__attribute__((unused)) static inline void command_p2(int cmd)
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{
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sdram_dfii_pi2_command_write(cmd);
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sdram_dfii_pi2_command_issue_write(1);
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}
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__attribute__((unused)) static inline void command_p3(int cmd)
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{
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sdram_dfii_pi3_command_write(cmd);
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sdram_dfii_pi3_command_issue_write(1);
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}
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
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switch (phase) {
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case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
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case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
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case 2: return CSR_SDRAM_DFII_PI2_WRDATA_ADDR;
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case 3: return CSR_SDRAM_DFII_PI3_WRDATA_ADDR;
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default: return 0;
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}
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}
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static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
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switch (phase) {
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case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
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case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
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case 2: return CSR_SDRAM_DFII_PI2_RDDATA_ADDR;
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case 3: return CSR_SDRAM_DFII_PI3_RDDATA_ADDR;
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default: return 0;
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}
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}
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#define DDRX_MR_WRLVL_ADDRESS 1
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#define DDRX_MR_WRLVL_RESET 6
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#define DDRX_MR_WRLVL_BIT 7
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static inline void init_sequence(void)
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{
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/* Release reset */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(50000);
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/* Bring CKE high */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(0);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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cdelay(10000);
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/* Load Mode Register 2, CWL=6 */
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sdram_dfii_pi0_address_write(0x208);
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sdram_dfii_pi0_baddress_write(2);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 3 */
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sdram_dfii_pi0_address_write(0x0);
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sdram_dfii_pi0_baddress_write(3);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 1 */
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sdram_dfii_pi0_address_write(0x6);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 0, CL=7, BL=8 */
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sdram_dfii_pi0_address_write(0x930);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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/* ZQ Calibration */
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sdram_dfii_pi0_address_write(0x400);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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}
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#endif
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