Piotr Binkowski 3b0ec8f996 modules: add KVR21SE15S8/4 SO-DIMM		2020-02-26 12:59:53 +01:00
..
core	core/controller: cleanup ControllerSettings	2019-12-03 12:16:50 +01:00
frontend	frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid	2020-02-19 18:34:55 +01:00
phy	phy/usddrphy: add Ultrascale Plus support.	2020-02-25 10:36:56 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: add BitSlip module (with reduced latency)	2020-02-17 12:40:06 +01:00
dfii.py	global: improve presentation/readability	2019-11-30 10:53:11 +01:00
gen.py	litedram_gen: add missing ECP5DDRPHY constant	2020-02-22 19:23:28 +01:00
init.py	modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior)	2019-12-03 12:20:32 +01:00
modules.py	modules: add KVR21SE15S8/4 SO-DIMM	2020-02-26 12:59:53 +01:00