Florent Kermarrec 3c1ab76bbc litedram/common/tXXDController: only set reset to 1 when txxd is None. ... This avoids triggering a warning/error with Yosys.		2020-05-19 13:10:32 +02:00
..
core	core/crossbar: remove retro-compat > 6 months old.	2020-05-18 18:51:56 +02:00
frontend	frontend/bist: simplify and fix CDC using AsyncFIFO.	2020-04-14 18:13:33 +02:00
phy	Merge pull request #189 from daveshah1/ddr4_rdimm_init	2020-05-15 21:34:43 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	litedram/common/tXXDController: only set reset to 1 when txxd is None.	2020-05-19 13:10:32 +02:00
dfii.py	dfii: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:47 +02:00
gen.py	litedram_gen: pass FPGA speedgrade to iodelay_pll.	2020-05-14 11:44:32 +02:00
init.py	test/reference: update.	2020-05-19 08:16:11 +02:00
modules.py	modules: fix SDRAMRegisteredModule.	2020-05-15 21:39:00 +02:00