35 lines
1.7 KiB
YAML
35 lines
1.7 KiB
YAML
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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{
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# General ------------------------------------------------------------------
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -1, # FPGA speedgrade
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"memtype": "DDR2", # DRAM type
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# PHY ----------------------------------------------------------------------
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"cmd_delay": 0, # Command additional delay (in taps)
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"cmd_latency": 0, # Command additional latency
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"sdram_module": "MT47H64M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 100e6, # Input clock frequency
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"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports_nb": 2, # Number of user ports
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"user_ports_type": "axi", # Type of ports (axi, wishbone, native)
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"user_ports_id_width": 32, # AXI identifier width
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# CSR Port -----------------------------------------------------------------
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"csr_expose": "False", # Expose CSR bus as I/Os
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"csr_align" : 32, # CSR alignment
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}
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