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litedram
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5aaffb7c16
litedram
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litedram
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Florent Kermarrec
5aaffb7c16
phy/s7ddrphy: remove dqs_i/dqs_i_delayed (no longer used).
2020-09-29 19:00:25 +02:00
..
core
core/multiplexer/steerel_sel: add support for dynamic rd/rdcmd/wr/wrcmd phases.
2020-09-14 18:40:58 +02:00
frontend
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
phy
phy/s7ddrphy: remove dqs_i/dqs_i_delayed (no longer used).
2020-09-29 19:00:25 +02:00
__init__.py
update code, start bankmachine refactoring and remove old code (will be rewritten)
2015-09-15 10:22:39 +02:00
common.py
s7ddrphy/usddrphy: add cmd_delay parameter and pass cmd_latency/cmd_delay to PhySettings/Software.
2020-09-07 18:50:01 +02:00
dfii.py
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
gen.py
litedram/gen: update LiteDRAMECP5DDRPHYCRG (AsyncResetSynchronizer integrated in PLL).
2020-09-01 13:58:16 +02:00
init.py
phy/usddrphy: reduce BitSlip cycles to 1 sys_clk.
2020-09-24 13:36:02 +02:00
modules.py
modules: remove unnecessary memtypes.
2020-09-01 13:43:09 +02:00