litedram/examples
2021-10-07 13:44:36 +02:00
..
arty.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00
genesys2.yml
kcu105.yml
nexys4ddr.yml
ulx3s.yml
versa_ecp5.yml examples/versa_ecp5: Fix memtype. 2021-10-07 13:44:36 +02:00
xcu1525.yml litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 2021-09-16 17:01:00 +02:00