255 lines
9.0 KiB
Python
Executable File
255 lines
9.0 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex.boards.platforms import kcu105
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import EDY4016A
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from litedram.phy import usddrphy
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
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pll.expose_drp()
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys)
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sys_clk_counter = Signal(32)
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self.sync += sys_clk_counter.eq(sys_clk_counter + 1)
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self.sys_clk_counter = CSRStatus(32)
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self.comb += self.sys_clk_counter.status.eq(sys_clk_counter)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6)):
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platform = kcu105.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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integrated_rom_size = 0x8000,
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integrated_rom_mode = "rw",
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csr_data_width = 32,
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uart_name = "crossover")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6,
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cmd_latency = 1)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = EDY4016A(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = 0x40000000,
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)
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# Ethebone ---------------------------------------------------------------------------------
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self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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self.add_csr("ethphy")
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
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self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Bench Test ---------------------------------------------------------------------------------------
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def bench_test():
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import time
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from litex import RemoteClient
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wb = RemoteClient()
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wb.open()
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# # #
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class SoCCtrl:
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@staticmethod
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def reboot():
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wb.regs.ctrl_reset.write(1)
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@staticmethod
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def load_rom(filename):
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i)
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class ClkReg1:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.low_time = (value >> 0) & (2**6 - 1)
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self.high_time = (value >> 6) & (2**6 - 1)
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self.reserved = (value >> 12) & (2**1 - 1)
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self.phase_mux = (value >> 13) & (2**3 - 1)
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def pack(self):
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value = (self.low_time << 0)
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value |= (self.high_time << 6)
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value |= (self.reserved << 12)
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value |= (self.phase_mux << 13)
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return value
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def __repr__(self):
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s = "ClkReg1:\n"
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s += " low_time: {:d}\n".format(self.low_time)
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s += " high_time: {:d}\n".format(self.high_time)
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s += " reserved: {:d}\n".format(self.reserved)
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s += " phase_mux: {:d}".format(self.phase_mux)
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return s
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class ClkReg2:
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def __init__(self, value = 0):
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self.unpack(value)
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def unpack(self, value):
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self.delay_time = (value >> 0) & (2**6 - 1)
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self.no_count = (value >> 6) & (2**1 - 1)
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self.edge = (value >> 7) & (2**1 - 1)
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self.mx = (value >> 8) & (2**2 - 1)
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self.frac_wf_r = (value >> 10) & (2**1 - 1)
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self.frac_en = (value >> 11) & (2**1 - 1)
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self.frac = (value >> 12) & (2**3 - 1)
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self.reserved = (value >> 15) & (2**1 - 1)
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def pack(self):
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value = (self.delay_time << 0)
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value |= (self.no_count << 6)
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value |= (self.edge << 7)
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value |= (self.mx << 8)
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value |= (self.frac_wf_r << 10)
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value |= (self.frac_en << 11)
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value |= (self.frac << 12)
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value |= (self.reserved << 15)
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return value
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def __repr__(self):
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s = "ClkReg2:\n"
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s += " delay_time: {:d}\n".format(self.delay_time)
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s += " no_count: {:d}\n".format(self.no_count)
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s += " edge: {:d}\n".format(self.edge)
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s += " mx: {:d}\n".format(self.mx)
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s += " frac_wf_r: {:d}\n".format(self.frac_wf_r)
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s += " frac_en: {:d}\n".format(self.frac_en)
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s += " frac: {:d}\n".format(self.frac)
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s += " reserved: {:d}".format(self.reserved)
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return s
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class USPLL:
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def reset(self):
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wb.regs.crg_main_pll_drp_reset.write(1)
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def read(self, adr):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_read.write(1)
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return wb.regs.crg_main_pll_drp_dat_r.read()
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def write(self, adr, value):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_dat_w.write(value)
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wb.regs.crg_main_pll_drp_write.write(1)
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# # #
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ctrl = SoCCtrl()
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ctrl.load_rom("build/kcu105/software/bios/bios.bin")
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ctrl.reset()
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vco_freq = 1e9
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uspll = USPLL()
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print("Dump Main PLL...")
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clkout0_clkreg1 = ClkReg1(uspll.read(0x08))
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print(clkout0_clkreg1)
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# TODO: add dynamic freq test.
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print("Reset SoC and get BIOS log...")
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ctrl.reset()
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start = time.time()
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while (time.time() - start) < 5:
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if wb.regs.uart_xover_rxempty.read() == 0:
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print("{:c}".format(wb.regs.uart_xover_rxtx.read()), end="")
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# # #
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wb.close()
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on KCU105")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--test", action="store_true", help="Run Test")
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args = parser.parse_args()
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if args.build or args.load:
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soc = BenchSoC()
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.test:
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bench_test()
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if __name__ == "__main__":
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main()
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