92 lines
3.0 KiB
Python
92 lines
3.0 KiB
Python
# This file is Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
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# License: BSD
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import random
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from migen import *
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def seed_to_data(seed, random=True, nbits=32):
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if nbits == 32:
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if random:
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return (seed * 0x31415979 + 1) & 0xffffffff
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else:
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return seed
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else:
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assert nbits%32 == 0
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data = 0
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for i in range(nbits//32):
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data = data << 32
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data |= seed_to_data(seed*nbits//32 + i, random, 32)
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return data
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class DRAMMemory:
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def __init__(self, width, depth, init=[]):
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self.width = width
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self.depth = depth
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self.mem = []
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for d in init:
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self.mem.append(d)
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for _ in range(depth-len(init)):
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self.mem.append(0)
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def show_content(self):
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for addr in range(self.depth):
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print("0x{:08x}: 0x{:08x}".format(addr, self.mem[addr]))
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@passive
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def read_handler(self, dram_port, rdata_valid_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.rdata.valid.eq(0)
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if pending:
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while prng.randrange(100) < rdata_valid_random:
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yield
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(self.mem[address%self.depth])
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yield
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yield dram_port.rdata.valid.eq(0)
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yield dram_port.rdata.data.eq(0)
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pending = 0
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elif (yield dram_port.cmd.valid):
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pending = not (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.addr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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@passive
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def write_handler(self, dram_port, wdata_ready_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.wdata.ready.eq(0)
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if pending:
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while (yield dram_port.wdata.valid) == 0:
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yield
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while prng.randrange(100) < wdata_ready_random:
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yield
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yield dram_port.wdata.ready.eq(1)
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yield
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self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
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yield dram_port.wdata.ready.eq(0)
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yield
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pending = 0
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yield
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elif (yield dram_port.cmd.valid):
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pending = (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.addr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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