Gwenhael Goavec-Merou 895b653a96 phy/gw2ddrphy: supressing warnings about unconnected and bit length.		2023-02-08 18:26:54 +01:00
..
core	core/refresher: Add assert on clk_freq/tREFI ratio.	2021-11-01 14:58:41 +01:00
frontend	frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade).	2023-01-16 11:21:47 +01:00
phy	phy/gw2ddrphy: supressing warnings about unconnected and bit length.	2023-02-08 18:26:54 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Allow for variable DQ/DQS ratio	2022-03-30 13:42:47 +02:00
dfii.py	dfii: Improve hardware/software control comments.	2022-03-28 14:27:41 +02:00
gen.py	gen: increase ROM size	2023-01-11 15:36:19 +01:00
init.py	init: define SDRAM_PHY_SUPPORTED_MEMORY	2023-01-09 16:03:09 +01:00
modules.py	Added AS4C4M16 residing on Arduino MKR Vidor 4000	2022-03-21 18:56:57 -07:00